JPS6417450A - Formation of bump - Google Patents

Formation of bump

Info

Publication number
JPS6417450A
JPS6417450A JP62172786A JP17278687A JPS6417450A JP S6417450 A JPS6417450 A JP S6417450A JP 62172786 A JP62172786 A JP 62172786A JP 17278687 A JP17278687 A JP 17278687A JP S6417450 A JPS6417450 A JP S6417450A
Authority
JP
Japan
Prior art keywords
bump
metallic
wiring
plating method
formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62172786A
Other languages
Japanese (ja)
Inventor
Hiroshi Kikuchi
Hitoshi Oka
Yoshiaki Wakadori
Keizo Matsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62172786A priority Critical patent/JPS6417450A/en
Publication of JPS6417450A publication Critical patent/JPS6417450A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Chemically Coating (AREA)

Abstract

PURPOSE:To obtain a bump which shows the same characteristics as in a conventional method, by performing a very small number of processes and using an electroless plating method to form a metallic bump. CONSTITUTION:A metallic wiring 1 is mounted on a surface, and a prescribed region of the wiring 1 on a substrate 3 is coated with an insulation layer 2, and a metallic bump 6 of a projecting shape is formed on the wiring 1. Then a metallic bump 6 is formed by an electroless plating method. The metallic bump 6 is made of one metal selected from gold, silver, copper, nickel, or cobalt. Thereupon, very small number of processes are used in comparison with the formation of the bump by a conventional electrical plating method, so that the bump showing the same characteristics as in the conventional method can be obtained.
JP62172786A 1987-07-13 1987-07-13 Formation of bump Pending JPS6417450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62172786A JPS6417450A (en) 1987-07-13 1987-07-13 Formation of bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62172786A JPS6417450A (en) 1987-07-13 1987-07-13 Formation of bump

Publications (1)

Publication Number Publication Date
JPS6417450A true JPS6417450A (en) 1989-01-20

Family

ID=15948327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62172786A Pending JPS6417450A (en) 1987-07-13 1987-07-13 Formation of bump

Country Status (1)

Country Link
JP (1) JPS6417450A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03209725A (en) * 1990-01-11 1991-09-12 Matsushita Electric Ind Co Ltd Method for forming bump of semiconductor device
DE19616373A1 (en) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Forming galvanically deposited contact bumps for integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03209725A (en) * 1990-01-11 1991-09-12 Matsushita Electric Ind Co Ltd Method for forming bump of semiconductor device
DE19616373A1 (en) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Forming galvanically deposited contact bumps for integrated circuits

Similar Documents

Publication Publication Date Title
JPS6461934A (en) Semiconductor device and manufacture thereof
CA2069363A1 (en) Thermal annealing of palladium alloys
JPS5534692A (en) Gold plated electronic parts and production thereof
ES443346A1 (en) Methods of forming conductors on substrates involving electroplating
EP0265629A3 (en) Printed circuit card fabrication process with nickel overplate
GB724379A (en) A method for making a predetermined metallic pattern on an insulating base
JPS6417450A (en) Formation of bump
JPS55138864A (en) Method of fabricating semiconductor assembling substrate
JPS647542A (en) Formation of bump
JPS54100931A (en) Electroless nickel plating
EP0344504A3 (en) Article comprising a polyimide and a metal layer and methods of making such articles
JPS5660038A (en) Semiconductor device
JPS5730353A (en) Semiconductor device
JPS5759343A (en) Surface treating method for circuit substrate
JPS54126468A (en) Production of resin-sealed semiconductor device
JPS5632748A (en) Ic with bump and manufacture thereof
JPS6420696A (en) Manufacture of film carrier board
JPS56129349A (en) Method of manufacturing airtight terminal
O'Hara Electrodepositing Precious Metal Alloys
JPS56148836A (en) Forming method for back electrode of semiconductor wafer
JPS6484224A (en) Electrode forming method
Sterling Electroplating Electrical Contacts
JPS56142886A (en) Tin plating method for aluminum alloy
JPS6417451A (en) Semiconductor device
GB1394062A (en) Semi-conductor devices