JPS5632748A - Ic with bump and manufacture thereof - Google Patents

Ic with bump and manufacture thereof

Info

Publication number
JPS5632748A
JPS5632748A JP10797579A JP10797579A JPS5632748A JP S5632748 A JPS5632748 A JP S5632748A JP 10797579 A JP10797579 A JP 10797579A JP 10797579 A JP10797579 A JP 10797579A JP S5632748 A JPS5632748 A JP S5632748A
Authority
JP
Japan
Prior art keywords
bump
substrate
tin
plated
coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10797579A
Other languages
Japanese (ja)
Inventor
Kenichi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP10797579A priority Critical patent/JPS5632748A/en
Publication of JPS5632748A publication Critical patent/JPS5632748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemically Coating (AREA)

Abstract

PURPOSE:To simplify the steps of treating a substrate on which an IC with a bump is carried by employing a bump coated with a tin coating by an electroless plating process on the copper bump as a bump when bonding the IC on the substrate, thereby eliminating shortcircuit or the like thereat. CONSTITUTION:An aluminum wiring layer 1 is formed on the substrate, and is surrounded by an insulating protective film 2, and a barrier metallic film 3 of Cr of the like is coated from the surface of the layer 1 over the end of the film 2. Then, a plating metallic film 4 is laminated thereon, the thick copper bump 5 is precipitated thereon by plating, and the exposed surface of the bump 5 is electrolessly plated while coating other portion with positive type photoresist to thus form the tin coating 6 thereon. In this manner, there can be used a substrate plated by Au as the substrate, the wire may not be shortcircuited due to tin whisker when using a tin- plated substrate, the treatment thereafter may also be eliminated, and the reliability of the IC may be consequently improved.
JP10797579A 1979-08-24 1979-08-24 Ic with bump and manufacture thereof Pending JPS5632748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10797579A JPS5632748A (en) 1979-08-24 1979-08-24 Ic with bump and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10797579A JPS5632748A (en) 1979-08-24 1979-08-24 Ic with bump and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5632748A true JPS5632748A (en) 1981-04-02

Family

ID=14472798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10797579A Pending JPS5632748A (en) 1979-08-24 1979-08-24 Ic with bump and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5632748A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6116486A (en) * 1984-06-29 1986-01-24 住友電気工業株式会社 Method of forming crosslinked polyethylene insulated power cable connector
JP2009124130A (en) * 2007-11-16 2009-06-04 Hwabeak Engineering Co Ltd Copper pole-tin bump formed in semiconductor chip, and its forming method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6116486A (en) * 1984-06-29 1986-01-24 住友電気工業株式会社 Method of forming crosslinked polyethylene insulated power cable connector
JPH0247827B2 (en) * 1984-06-29 1990-10-23 Sumitomo Electric Industries
JP2009124130A (en) * 2007-11-16 2009-06-04 Hwabeak Engineering Co Ltd Copper pole-tin bump formed in semiconductor chip, and its forming method
US7781325B2 (en) * 2007-11-16 2010-08-24 Hwaback Engineering Co., Ltd. Copper pillar tin bump on semiconductor chip and method of forming the same
TWI450336B (en) * 2007-11-16 2014-08-21 Hwaback Enginnering Co Ltd Copper pillar tin bump on semiconductor chip and method of forming of the same

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