JPS56161664A - Manufacture of lead for connecting semiconductor device - Google Patents

Manufacture of lead for connecting semiconductor device

Info

Publication number
JPS56161664A
JPS56161664A JP6474680A JP6474680A JPS56161664A JP S56161664 A JPS56161664 A JP S56161664A JP 6474680 A JP6474680 A JP 6474680A JP 6474680 A JP6474680 A JP 6474680A JP S56161664 A JPS56161664 A JP S56161664A
Authority
JP
Japan
Prior art keywords
layer
lead
gold
conductor
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6474680A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamanouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6474680A priority Critical patent/JPS56161664A/en
Publication of JPS56161664A publication Critical patent/JPS56161664A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance the reliability of the connection of a bump electrode to a semiconductor device by selectively plating gold pattern on a copper layer bonded to an electrically insulating film main surface, then removing the unnecessary copper layer to form a metallic lead and facilitating the design and manufacture of the pattern. CONSTITUTION:After a copper foil 3 is bonded to the main surface of a polyimide film 1 or the like, a resist 4 is covered on the part except the wiring conductor. Then, a gold layer 14 is electrically plated on the conductor, the back surface of the film 1 is photoetched, and a window 2 is formed. Thereafter, the layer 14 is used as a mask, the unnecessary copper foil 3 is etched and removed as a wiring conductor 16. Subsequently, a bump electrode 10 and the gold layer 14 formed, for example, on an Si substrate 7 are thermally pressed to connect the element to the conductor 16. Since the gold plating layer can be thus increased in thickness, the lead connection can be improved in reliability. Since plating wires are not particularly necessary, it can increase the degree of the freedom of design and can reduce the size of the lead.
JP6474680A 1980-05-16 1980-05-16 Manufacture of lead for connecting semiconductor device Pending JPS56161664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6474680A JPS56161664A (en) 1980-05-16 1980-05-16 Manufacture of lead for connecting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6474680A JPS56161664A (en) 1980-05-16 1980-05-16 Manufacture of lead for connecting semiconductor device

Publications (1)

Publication Number Publication Date
JPS56161664A true JPS56161664A (en) 1981-12-12

Family

ID=13267023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6474680A Pending JPS56161664A (en) 1980-05-16 1980-05-16 Manufacture of lead for connecting semiconductor device

Country Status (1)

Country Link
JP (1) JPS56161664A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438222A (en) * 1989-08-28 1995-08-01 Semiconductor Energy Laboratory Co., Ltd. Electronic device with plural pad connection of semiconductor chip to leads
US6297142B1 (en) 1998-03-18 2001-10-02 Hitachi Cable Ltd. Method for bonding a semiconductor chip to a lead-patterning substrate using a gold/tin alloy

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438222A (en) * 1989-08-28 1995-08-01 Semiconductor Energy Laboratory Co., Ltd. Electronic device with plural pad connection of semiconductor chip to leads
US6297142B1 (en) 1998-03-18 2001-10-02 Hitachi Cable Ltd. Method for bonding a semiconductor chip to a lead-patterning substrate using a gold/tin alloy
US6426548B1 (en) * 1998-03-18 2002-07-30 Hitachi Cable Ltd. Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same
US6433409B2 (en) 1998-03-18 2002-08-13 Hitachi Cable Ltd. Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same

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