KR930001299A - 다층유리-세라믹 회로판의 제조방법 - Google Patents

다층유리-세라믹 회로판의 제조방법 Download PDF

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KR930001299A
KR930001299A KR1019920010586A KR920010586A KR930001299A KR 930001299 A KR930001299 A KR 930001299A KR 1019920010586 A KR1019920010586 A KR 1019920010586A KR 920010586 A KR920010586 A KR 920010586A KR 930001299 A KR930001299 A KR 930001299A
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powder
ceramic
green sheet
glass
copper
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KR1019920010586A
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KR960001354B1 (ko
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히또시 스즈끼
와따루 야마기시
고이찌 니와
가오루 하시모또
노부오 가메하라
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세끼사와 요시
후지쓰 가부시끼가이샤
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0263—Details about a collection of particles
    • H05K2201/0266—Size distribution
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1126—Firing, i.e. heating a powder or paste above the melting temperature of at least one of its constituents
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
    • H05K3/1291—Firing or sintering at relative high temperatures for patterns on inorganic boards, e.g. co-firing of circuits on green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)

Abstract

내용 없음

Description

다층 유리-세라믹 회로판의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 유리-세라믹 그린시트의 관통공에 관통접점 형성물질을 충전하기 위한 구조를 도시한 사시도.
제2도는 구리분말과 유리-세라믹과의 혼합물에 대한 구리 및 알루미나분말의 혼합물로된 분말 압축물의 소결 수축성질을 도시한 그래프.
제3도는 구리분말과 유리-세라믹에 대한 구리풀의 소결 수축성질을 도시한 그래프.
제4도는 2레벨의 알루미나 입자크기에 대한 알루미나 함량의 함수로서 구리 및 알루미나분말의 흔합물의 발화 압축물의 전기적 저항을 도시한 그래프.
제5도는 알루미나 입자크기의 함수로서 구리 및 알루미나분말의 혼합물의 발화 압축물의 전기적 저항을 도시한 그래프.
제6도는 평균 구리 입자크기의 함수로서 유리-세라믹 그린시트의 관통공내에만 충전된 구리분말의 패킹밀도를 도시한 그래프.
제7도는 평균 알루미나 입자크기의 함수로서 유리-세라믹 그린시트의 관통공내에 충전된 구리 및 알루미나분말의 흔합물의 패킹밀도를 도시한 그래프.
제8도는 구리분말과 유리-세라믹 혼합물에 대한 구리 및 뮬라이트분말의 혼합물로된 분말 압축물의 소결 수축성질을 도시한 그래프.
제9도는 구리분말과 유리-세라믹 흔합물에 대한 구리 및 실리카 분말의 혼합물로 된 분말 압축물의 소결 수축성질을 도시한 그래프이다.

Claims (7)

  1. 구리전도체를 갖는 다층 유리-세라믹 회로판의 제조방법에 있어서 : 관통접점이 형성되는 곳에서 유리-세라믹 그린시트내에 관통공을 형성시키는 단계 ; 상기의 관통공에 세라믹 분말이 혼합된 구리분말의 분말 혼합물을 충전하되, 상기의 구리 분말과 세라믹 분말은 관통공내에 충전될 때 유리-세라믹 그린시트의 것보다 큰 패킹밀도를 제공하는 분말입자크기를 갖도록 하는 단계 ; 그린시트위에 회로전도체 패턴을 형성하기 위해 분말 혼합물이 충전된 관통공을 갖는 그린시트위에 전도체풀을 인쇄하는 단계 ; 적층 동체를 형성하기 위해서 전도체 패턴을 갖는 다수의 그린시트를 적층하는 단계 ; 적층 동체를 가열하여 그로부터 결합제를 제거하고 적층 동체를 예비 발화시키는 단계 ; 및 예비 발화된 동체를 발화시키는 단계로 구성되는 다층 유리-세라믹 회로판의 제조방법.
  2. 제1항에 있어서, 상기의 유리-세라믹 그린시트는 약 50-60%의 상대밀도를 갖으며, 상기의 구리분말과 세라믹분말은 상기의 관통공에 충전될 때 약 55-65%의 패킹 밀도를 제공하는 분말입자크기를 갖음을 특징으로 하는 다층 유리-세라믹 회로판의 제조방법.
  3. 제1항에 있어서, 상기의 구리분말은 0.3-8μm의 분말입자크기를 갖으며, 상기의 세라믹 분말은 0.1-1μm의 분말입자크기를 갖음을 특징으로 하는 다층 유리-세라믹 회로판의 제조방법.
  4. 제1항에 있어서, 상기의 세라믹 분말은 상기의 구리분말보다 작은 분말입자크기를 갖음을 특징으로 하는 다층 유리-세라믹 회로판의 제조방법.
  5. 제1항에 있어서, 상기의 그린시트는 발화시 약 700℃∼1000℃의 온도에서 수축되기 시작함을 특징으로 하는 다층 유리-세라믹 회로판의 제조방법.
  6. 제1항에 있어서, 상기의 세라믹분말은 알루미나, 실리카 및 뮬라이트로 된 기에서 선택되는 세라믹으로 구성됨을 특징으로 하는 다층 유리-세라믹 회로판의 제조방법.
  7. 제1항에 있어서, 상기의 분말 혼합물은 상기의 구리분말과 상기의 세라믹 분말을 소정의 비율로 흔합하여, 상기 구리분말만을 발화시킬 때 600℃ 근처의 온도에서 발생되는 상당량의 수축을 억제하고 상기 분말 혼합물의 발화시 1000℃ 근처의 온도에서 수축을 완료하도록 제조됨을 특징으로 하는 다층 유리-세라믹 회로판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920010586A 1991-06-18 1992-06-18 다층 유리-세라믹 회로판의 제조방법 KR960001354B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-146136 1991-06-18
JP3146136A JP2584911B2 (ja) 1991-06-18 1991-06-18 ガラス−セラミック多層回路基板の製造方法

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KR930001299A true KR930001299A (ko) 1993-01-16
KR960001354B1 KR960001354B1 (ko) 1996-01-26

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US (1) US5287620A (ko)
EP (1) EP0519676B1 (ko)
JP (1) JP2584911B2 (ko)
KR (1) KR960001354B1 (ko)
CA (1) CA2070308C (ko)
DE (1) DE69203544T2 (ko)

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JPH03212993A (ja) * 1990-01-18 1991-09-18 Fujitsu Ltd 多層セラミック回路基板の製造方法とビア形成方法

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EP0519676A2 (en) 1992-12-23
DE69203544T2 (de) 1996-01-11
CA2070308C (en) 1996-06-25
EP0519676B1 (en) 1995-07-19
JPH04369899A (ja) 1992-12-22
EP0519676A3 (en) 1993-05-12
CA2070308A1 (en) 1992-12-19
DE69203544D1 (de) 1995-08-24
JP2584911B2 (ja) 1997-02-26
KR960001354B1 (ko) 1996-01-26
US5287620A (en) 1994-02-22

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