KR920702794A - 텅스텐 실리사이드 화학 기상 증착 - Google Patents

텅스텐 실리사이드 화학 기상 증착

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Publication number
KR920702794A
KR920702794A KR1019910702017A KR910702017A KR920702794A KR 920702794 A KR920702794 A KR 920702794A KR 1019910702017 A KR1019910702017 A KR 1019910702017A KR 910702017 A KR910702017 A KR 910702017A KR 920702794 A KR920702794 A KR 920702794A
Authority
KR
South Korea
Prior art keywords
tungsten silicide
millitorr
vapor deposition
chemical vapor
mixture
Prior art date
Application number
KR1019910702017A
Other languages
English (en)
Inventor
조셉 티이. 힐만
제이. 비이. 프리스
Original Assignee
원본미기재
비시티 스펙트럼 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 원본미기재, 비시티 스펙트럼 인코포레이티드 filed Critical 원본미기재
Publication of KR920702794A publication Critical patent/KR920702794A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/42—Silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Abstract

내용 없음

Description

텅스텐 실리사이드 화학 기상 증착
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 WF6흐름율과 막의 비저항의 관계에 의하여 본 발명을 설명한 그래프이다.
제2도는 WF6흐름율과 막의 균일성의 관계에 의하여 본 발명을 설명한 그래프이다.
제3도는 WF6흐름율과 막의 증착율의 관계에 의하여 본 발명을 설명한 그래프이다.

Claims (3)

  1. WF6와 SiH2Cl2의 가스혼합물이 흐르는 챔버내에서 450℃ 보다 높은 온도로 가열된 웨이퍼상에 텅스텡 실리사이드 층을 증착시키기 위한 방법에 있어서, 10%이하의 디실란을 상기 혼합물에 첨가하는 단계를 포함함을 특징으로 하는 방법.
  2. 디클로로실란과 육플루오르화 텅스텐의 가스혼합물을 반응 챔버에 공급하는 단계를 포함하는, 상기 반응 챔버내에서 반도체 웨이퍼 상에 텅스텐 실리사이드를 증착시키기 위항 방법에 있어서, a.상기 혼합물의 10%이하를 함유하는 디실란을 상기 혼합물에 첨가하는 단계; b.상기 챔버내의 압력을 30 내지 300밀리토르로 유지시키는 단계; 및 c.상기 텅스텐 실리사이드 층을 증착시키기 위해 상기 웨이퍼를 450℃내지 650℃의 온도로 가열시키는 단계를 포함함을 특징으로 하는 방법.
  3. 제2항에 있어서, 상기 웨이퍼는 약 560℃의 온도로 가열되고, 상기 디클로로실란의 분압은 약 82 밀리토르이고, 상기 육플르오르화 텅스텐의 분압은 약 4 밀리토르이고, 상기 디실란의 분압은 약 4밀리토르임을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910702017A 1990-05-04 1991-05-03 텅스텐 실리사이드 화학 기상 증착 KR920702794A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/519,538 US4966869A (en) 1990-05-04 1990-05-04 Tungsten disilicide CVD
US07/519538 1990-05-04
PCT/US1991/003049 WO1991017566A1 (en) 1990-05-04 1991-05-03 Tungsten disilicide cvd

Publications (1)

Publication Number Publication Date
KR920702794A true KR920702794A (ko) 1992-10-06

Family

ID=24068739

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910702017A KR920702794A (ko) 1990-05-04 1991-05-03 텅스텐 실리사이드 화학 기상 증착

Country Status (6)

Country Link
US (1) US4966869A (ko)
JP (1) JPH05504660A (ko)
KR (1) KR920702794A (ko)
DE (1) DE4190885T (ko)
NL (1) NL9120003A (ko)
WO (1) WO1991017566A1 (ko)

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JP2723396B2 (ja) * 1991-09-19 1998-03-09 シャープ株式会社 不揮発性メモリ装置の製造方法
JP3163687B2 (ja) * 1991-11-12 2001-05-08 富士通株式会社 化学気相成長装置及び化学気相成長膜形成方法
US5231056A (en) * 1992-01-15 1993-07-27 Micron Technology, Inc. Tungsten silicide (WSix) deposition process for semiconductor manufacture
JP2599560B2 (ja) * 1992-09-30 1997-04-09 インターナショナル・ビジネス・マシーンズ・コーポレイション ケイ化タングステン膜形成方法
US5643633A (en) * 1992-12-22 1997-07-01 Applied Materials, Inc. Uniform tungsten silicide films produced by chemical vapor depostiton
US5500249A (en) * 1992-12-22 1996-03-19 Applied Materials, Inc. Uniform tungsten silicide films produced by chemical vapor deposition
US6090706A (en) * 1993-06-28 2000-07-18 Applied Materials, Inc. Preconditioning process for treating deposition chamber prior to deposition of tungsten silicide coating on active substrates therein
US5482749A (en) * 1993-06-28 1996-01-09 Applied Materials, Inc. Pretreatment process for treating aluminum-bearing surfaces of deposition chamber prior to deposition of tungsten silicide coating on substrate therein
JPH07176484A (ja) * 1993-06-28 1995-07-14 Applied Materials Inc 窒化アルミニューム面を有するサセプタをサセプタの浄化後珪化タングステンで処理することによって半導体ウエハ上に珪化タングステンを一様に堆積する方法
USRE39895E1 (en) 1994-06-13 2007-10-23 Renesas Technology Corp. Semiconductor integrated circuit arrangement fabrication method
DE69518710T2 (de) * 1994-09-27 2001-05-23 Applied Materials Inc Verfahren zum Behandeln eines Substrats in einer Vakuumbehandlungskammer
JPH08153804A (ja) * 1994-09-28 1996-06-11 Sony Corp ゲート電極の形成方法
EP0746027A3 (en) * 1995-05-03 1998-04-01 Applied Materials, Inc. Polysilicon/tungsten silicide multilayer composite formed on an integrated circuit structure, and improved method of making same
KR100341247B1 (ko) * 1995-12-29 2002-11-07 주식회사 하이닉스반도체 반도체소자의제조방법
EP0785574A3 (en) 1996-01-16 1998-07-29 Applied Materials, Inc. Method of forming tungsten-silicide
US6335280B1 (en) 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
TW396646B (en) 1997-09-11 2000-07-01 Lg Semicon Co Ltd Manufacturing method of semiconductor devices
KR100425147B1 (ko) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 반도체소자의제조방법
DE10134461B4 (de) * 2001-07-16 2006-05-18 Infineon Technologies Ag Prozess zur Abscheidung von WSix-Schichten auf hoher Topografie mit definierter Stöchiometrie und dadurch hergestelltes Bauelement
US6913670B2 (en) * 2002-04-08 2005-07-05 Applied Materials, Inc. Substrate support having barrier capable of detecting fluid leakage
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Also Published As

Publication number Publication date
DE4190885T (ko) 1992-12-10
JPH05504660A (ja) 1993-07-15
US4966869A (en) 1990-10-30
NL9120003A (nl) 1992-05-06
WO1991017566A1 (en) 1991-11-14

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