KR920022383A - Cmos의 단차 없는 두개의 웰 제조방법 - Google Patents
Cmos의 단차 없는 두개의 웰 제조방법 Download PDFInfo
- Publication number
- KR920022383A KR920022383A KR1019910007187A KR910007187A KR920022383A KR 920022383 A KR920022383 A KR 920022383A KR 1019910007187 A KR1019910007187 A KR 1019910007187A KR 910007187 A KR910007187 A KR 910007187A KR 920022383 A KR920022383 A KR 920022383A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- photoresist
- substrate
- well
- cmos
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims 4
- 229920002120 photoresistant polymer Polymers 0.000 claims 8
- 239000000758 substrate Substances 0.000 claims 8
- 238000005530 etching Methods 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/07—Guard rings and cmos
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2D도는 본 발명의 제1실시예에 의해 CMOS의 단차없는 두개의 웰 제조방법을 도시한 단면도.
Claims (3)
- CMOS의 두개의 웰 제조방법에 있어서, 기판상부에 두꺼운 산화막을 형성하고, 그 상부에 포토레지스트를 도포한다음, N웰 마스크를 이용하여 예정된 얼라인키영역과 N웰 영역의 포토레지스트를 제거하고 그 하부이 두꺼운 산화막을 소정두께 식각하여 얇은 두께의 산화막으로 형성하는 단계와, N형 불순물을 얇은 산화막을 통하여 기판으로 이온주입하는 단계와, 상기 포토레지스트를 완전히 제거하고 다시 포토레지스트를 전체적으로 도포한후, P웰 마스크를 이용하여 예정된 P웰 영역의 포토레지스트를 제거하고, 그 하부의 두꺼운 산화막을 소정두께 식각하여 얇은 두께의 산화막으로 형성하고 얼라인키 지역은 포토레지스트가 도포되어 있는 단계와, P형 불순물을 얇은 산화막을 통하여 기판으로 이온주입하는 단계와, 상기 포토레지스트를 제거하고 드라이브-인 공정으로 주입된 N형 불순물과 P형 불순물을 기판내부로 주입하여 N웰영역 및 P웰영역을 형성하고, 드라이브-인 공정시 얇은 산화막 상, 하부에 성장된 산화막을 모두 제거하는 단계로 이루어지는 것을 특징으로 하는 CMOS의 단차가 없는 두개의 웰 제조방법.
- 제1항에 있어서, 상기 P웰 마스크를 이용하여 예정된 P웰영역의 포토레지스트를 제거하고, 그 하부의 두꺼운 산화막을 소정두께 식각하여 얇은 두께의 산화막으로 형성하는 단계에서, P웰 마스크를 이용하는 대신에 N-ch 필드스톱 임플란트 마스크를 사용하는 것을 포함하는 것을 특징으로 하는 CMOS의 단차가 없는 두개의 웰 제조방법.
- 제1항에 있어서, 상기 기판 상부에 두꺼운 산화막을 형성하는 공정에서, 기판상부에 얇은 산화막을 형성하고 그 상부에 질화막을 형성하고 상기 공정단계로 진행하되 두꺼운 산화막을 소정두께 제거하는 공정대신 질화막을 제거하는 공정단계를 포함하는 것을 특징으로 하는 CMPS의 단차가 없는 두개의 웰 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910007187A KR940009997B1 (ko) | 1991-05-03 | 1991-05-03 | Cmos의 단차없는 두개의 웰 제조방법 |
ITTO920366A IT1259563B (it) | 1991-05-03 | 1992-04-28 | Metodo per la fabbricazione di un dispositivo cmos a doppio pozzetto |
US07/874,920 US5252510A (en) | 1991-05-03 | 1992-04-29 | Method for manufacturing a CMOS device having twin wells and an alignment key region |
DE4214302A DE4214302C2 (de) | 1991-05-03 | 1992-04-30 | Verfahren zur Herstellung einer CMOS-Struktur mit Doppelwannen |
DE4244882A DE4244882C2 (de) | 1991-05-03 | 1992-04-30 | Verfahren zur Herstellung einer CMOS-Struktur mit Doppelwannen |
JP4112012A JP2521611B2 (ja) | 1991-05-03 | 1992-05-01 | ツインウェルを有するcmosの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910007187A KR940009997B1 (ko) | 1991-05-03 | 1991-05-03 | Cmos의 단차없는 두개의 웰 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920022383A true KR920022383A (ko) | 1992-12-19 |
KR940009997B1 KR940009997B1 (ko) | 1994-10-19 |
Family
ID=19314068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910007187A KR940009997B1 (ko) | 1991-05-03 | 1991-05-03 | Cmos의 단차없는 두개의 웰 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5252510A (ko) |
JP (1) | JP2521611B2 (ko) |
KR (1) | KR940009997B1 (ko) |
IT (1) | IT1259563B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100450566B1 (ko) * | 2001-12-24 | 2004-09-30 | 동부전자 주식회사 | 씨모오스형 트랜지스터 제조 방법 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3174786B2 (ja) * | 1991-05-31 | 2001-06-11 | 富士通株式会社 | 半導体装置の製造方法 |
JP3404873B2 (ja) * | 1994-03-25 | 2003-05-12 | 株式会社デンソー | 半導体装置の製造方法 |
TW322629B (en) * | 1996-09-06 | 1997-12-11 | Holtek Microelectronics Inc | Manufacturing method of integrated circuit alignment mark |
TW311273B (en) * | 1996-09-26 | 1997-07-21 | Holtek Microelectronics Inc | Manufacturing method of high step alignment mark |
US5776816A (en) * | 1996-10-28 | 1998-07-07 | Holtek Microelectronics, Inc. | Nitride double etching for twin well align |
US5688710A (en) * | 1996-11-27 | 1997-11-18 | Holtek Microelectronics, Inc. | Method of fabricating a twin - well CMOS device |
KR100266652B1 (ko) * | 1997-12-29 | 2000-11-01 | 김영환 | 반도체 소자의 트윈 웰 형성방법 |
US6133077A (en) | 1998-01-13 | 2000-10-17 | Lsi Logic Corporation | Formation of high-voltage and low-voltage devices on a semiconductor substrate |
US6093585A (en) * | 1998-05-08 | 2000-07-25 | Lsi Logic Corporation | High voltage tolerant thin film transistor |
KR100554201B1 (ko) * | 1999-03-29 | 2006-02-22 | 페어차일드코리아반도체 주식회사 | 씨디모스 제조방법 |
US6573151B1 (en) * | 2000-08-22 | 2003-06-03 | Advanced Micro Devices, Inc. | Method of forming zero marks |
KR100480593B1 (ko) * | 2002-01-04 | 2005-04-06 | 삼성전자주식회사 | 활성 영역 한정용 얼라인 키를 가지는 반도체 소자 및 그제조 방법 |
US6596604B1 (en) * | 2002-07-22 | 2003-07-22 | Atmel Corporation | Method of preventing shift of alignment marks during rapid thermal processing |
KR100515057B1 (ko) * | 2003-01-10 | 2005-09-14 | 삼성전자주식회사 | 반도체 소자의 트렌치 소자분리막들 형성방법 |
US7435659B2 (en) * | 2005-02-28 | 2008-10-14 | Texas Instruments Incorporated | Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process |
JP3775508B1 (ja) * | 2005-03-10 | 2006-05-17 | 株式会社リコー | 半導体装置の製造方法及び半導体装置 |
JP4718961B2 (ja) | 2005-09-30 | 2011-07-06 | 株式会社東芝 | 半導体集積回路装置及びその製造方法 |
KR100734325B1 (ko) * | 2006-07-14 | 2007-07-02 | 삼성전자주식회사 | 반도체 소자의 제조방법 |
KR100850121B1 (ko) * | 2006-10-19 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 얼라인 키를 이용한 반도체 소자의 웰 제조 방법 |
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JPS57139921A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
US4599789A (en) * | 1984-06-15 | 1986-07-15 | Harris Corporation | Process of making twin well VLSI CMOS |
US4561170A (en) * | 1984-07-02 | 1985-12-31 | Texas Instruments Incorporated | Method of making field-plate isolated CMOS devices |
US4696092A (en) * | 1984-07-02 | 1987-09-29 | Texas Instruments Incorporated | Method of making field-plate isolated CMOS devices |
US4558508A (en) * | 1984-10-15 | 1985-12-17 | International Business Machines Corporation | Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step |
US4584027A (en) * | 1984-11-07 | 1986-04-22 | Ncr Corporation | Twin well single mask CMOS process |
US4677739A (en) * | 1984-11-29 | 1987-07-07 | Texas Instruments Incorporated | High density CMOS integrated circuit manufacturing process |
JPS6246552A (ja) * | 1985-08-23 | 1987-02-28 | Toshiba Corp | 半導体装置の製造方法 |
US4767721A (en) * | 1986-02-10 | 1988-08-30 | Hughes Aircraft Company | Double layer photoresist process for well self-align and ion implantation masking |
US4889825A (en) * | 1986-03-04 | 1989-12-26 | Motorola, Inc. | High/low doping profile for twin well process |
US4929565A (en) * | 1986-03-04 | 1990-05-29 | Motorola, Inc. | High/low doping profile for twin well process |
JPH01161752A (ja) * | 1987-12-18 | 1989-06-26 | Toshiba Corp | 半導体装置製造方法 |
US4925806A (en) * | 1988-03-17 | 1990-05-15 | Northern Telecom Limited | Method for making a doped well in a semiconductor substrate |
JPH01241158A (ja) * | 1988-03-23 | 1989-09-26 | Toshiba Corp | 半導体集積回路の製造方法 |
US4951114A (en) * | 1988-12-05 | 1990-08-21 | Raytheon Company | Complementary metal electrode semiconductor device |
JPH0377377A (ja) * | 1989-08-19 | 1991-04-02 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPH03129818A (ja) * | 1989-10-16 | 1991-06-03 | Nec Corp | 半導体装置の製造方法 |
US5132241A (en) * | 1991-04-15 | 1992-07-21 | Industrial Technology Research Institute | Method of manufacturing minimum counterdoping in twin well process |
-
1991
- 1991-05-03 KR KR1019910007187A patent/KR940009997B1/ko not_active IP Right Cessation
-
1992
- 1992-04-28 IT ITTO920366A patent/IT1259563B/it active IP Right Grant
- 1992-04-29 US US07/874,920 patent/US5252510A/en not_active Expired - Lifetime
- 1992-05-01 JP JP4112012A patent/JP2521611B2/ja not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100450566B1 (ko) * | 2001-12-24 | 2004-09-30 | 동부전자 주식회사 | 씨모오스형 트랜지스터 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
IT1259563B (it) | 1996-03-20 |
US5252510A (en) | 1993-10-12 |
KR940009997B1 (ko) | 1994-10-19 |
ITTO920366A1 (it) | 1993-10-28 |
JP2521611B2 (ja) | 1996-08-07 |
JPH05160355A (ja) | 1993-06-25 |
ITTO920366A0 (it) | 1992-04-28 |
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