KR910021020A - 프로그래머블 지연회로 - Google Patents

프로그래머블 지연회로 Download PDF

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Publication number
KR910021020A
KR910021020A KR1019910007275A KR910007275A KR910021020A KR 910021020 A KR910021020 A KR 910021020A KR 1019910007275 A KR1019910007275 A KR 1019910007275A KR 910007275 A KR910007275 A KR 910007275A KR 910021020 A KR910021020 A KR 910021020A
Authority
KR
South Korea
Prior art keywords
delay circuit
delayed
input
programmable delay
output terminal
Prior art date
Application number
KR1019910007275A
Other languages
English (en)
Other versions
KR0153245B1 (ko
Inventor
다이스께 무라가미
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR910021020A publication Critical patent/KR910021020A/ko
Application granted granted Critical
Publication of KR0153245B1 publication Critical patent/KR0153245B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6257—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means
    • H03K17/6264—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means using current steering means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00182—Layout of the delay element using bipolar transistors using constant current sources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00228—Layout of the delay element having complementary input and output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Abstract

내용 없음

Description

프로그래머블 지연회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 프로그래머블 지연회로의 기본구성의 블록회로도, 제4도 (제4A 및 제4B도)는 본 발명에 의한 프로그래머블 지연 회로의 일실시예의 회로도.

Claims (5)

  1. (a) 지연될 입력신호가 공급되는 입력단자와, (b) 캐스케이드로 접속된 복수의 스테이지의 N (N 2)개의 지연 회로와, (c) 이 복수의 스테이지의 지연회로사이에서 각 스테이지에 각각 접속되면서, 1쌍의 차동증폭기트랜지스터와, 공동전류원으로부터 상기 1쌍의 차동증폭기트랜지스터에 구동 전류를 공급하기 위한 전류스위치를 가진 복수의 자동증폭기와, (d) 상기 복수의 차동증폭기중 1쌍의 차동증폭기트랜지스터의 각 출력단자에 공통으로 접속된 공통출력단자와, (e) 상기 복수의 차동증폭기의 전류스위치를 각각 제어하기 위한 제어회로로 이루어지는 것을 특징으로 하는 프로그래머블 지연회로.
  2. 제1항에 있어서, 캐스케이드로 접속된 버퍼스테이지가 상기 복수의 차동증폭기의 출력과 상기 공통출력단자 사이에 배치되는 것을 특징으로 하는 프로그래머블 지연회로.
  3. 제2항에 있어서, 지연될 입력신호가 상기 출력단자에 직접 공급되는 것을 특징으로 하는 프로그래머블 지연회로.
  4. 제3항에 있어서, 지연될 신호가 입력되는 입력단자와 제1스테이지의 지연회로사이에 에미터 폴로어 스테이지가 접속되는 것을 특징으로 하는 프로그래머블 지연회로.
  5. 제4항에 있어서, 지연될 신호가 입력되는 상기 입력단자에 푸시풀신호가 공급되고, 푸시풀신호가 상기 공통 출력단자에서 소정의 지연시간만큼 지연되는 것을 특징으로 하는 프로그래머블 지연회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910007275A 1990-05-11 1991-05-06 프로그래머블 지연회로 KR0153245B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP02119792A JP3077813B2 (ja) 1990-05-11 1990-05-11 プログラマブル遅延回路
JP2-119792 1990-05-11
JP90-119,792 1990-05-11

Publications (2)

Publication Number Publication Date
KR910021020A true KR910021020A (ko) 1991-12-20
KR0153245B1 KR0153245B1 (ko) 1998-12-15

Family

ID=14770339

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910007275A KR0153245B1 (ko) 1990-05-11 1991-05-06 프로그래머블 지연회로

Country Status (5)

Country Link
US (1) US5144174A (ko)
EP (1) EP0456231B1 (ko)
JP (1) JP3077813B2 (ko)
KR (1) KR0153245B1 (ko)
DE (1) DE69124002T2 (ko)

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CA2070883A1 (en) * 1991-06-10 1992-12-11 Yasunori Kanai Waveform synthesizing circuit
JP2675455B2 (ja) * 1991-06-28 1997-11-12 三洋電機株式会社 可変遅延装置
JP3326619B2 (ja) * 1992-01-08 2002-09-24 ソニー株式会社 Ｐｗｍ回路
US5554950A (en) * 1992-02-04 1996-09-10 Brooktree Corporation Delay line providing an adjustable delay in response to binary input signals
FR2689339B1 (fr) * 1992-03-24 1996-12-13 Bull Sa Procede et dispositif de reglage de retard a plusieurs gammes.
US5347175A (en) * 1992-05-12 1994-09-13 The United States Of America As Represented By The Secretary Of Commerce Voltage comparator with reduced settling time
JP2595104Y2 (ja) * 1992-07-31 1999-05-24 安藤電気株式会社 差動ゲートによるタイミング調整回路
JP2595103Y2 (ja) * 1992-07-31 1999-05-24 安藤電気株式会社 差動ゲートによるタイミング調整回路
JP3550404B2 (ja) * 1992-09-10 2004-08-04 株式会社日立製作所 可変遅延回路及び可変遅延回路を用いたクロック信号供給装置
US5376849A (en) * 1992-12-04 1994-12-27 International Business Machines Corporation High resolution programmable pulse generator employing controllable delay
US5479091A (en) * 1992-12-11 1995-12-26 Texas Instruments Incorporated Output current reference circuit and method
US5376833A (en) * 1992-12-11 1994-12-27 Texas Instruments Incorporated Current driver circuit
DE69403974T2 (de) * 1993-02-25 1997-10-16 At & T Corp In einem grossen Bereich arbeitende veränderbare Verzögerungsleitung und Ringoszillator
US5694070A (en) * 1994-07-11 1997-12-02 Vitesse Semiconductor Corporation Distributed ramp delay generator
US5631491A (en) * 1994-09-27 1997-05-20 Fuji Electric Co., Ltd. Lateral semiconductor device and method of fixing potential of the same
US5777501A (en) * 1996-04-29 1998-07-07 Mosaid Technologies Incorporated Digital delay line for a reduced jitter digital delay lock loop
US6054889A (en) * 1997-11-11 2000-04-25 Trw Inc. Mixer with improved linear range
US6480548B1 (en) 1997-11-17 2002-11-12 Silicon Graphics, Inc. Spacial derivative bus encoder and decoder
JP4146965B2 (ja) 1999-05-17 2008-09-10 株式会社アドバンテスト 遅延信号生成装置および半導体試験装置
US6775339B1 (en) 1999-08-27 2004-08-10 Silicon Graphics, Inc. Circuit design for high-speed digital communication
US7031420B1 (en) 1999-12-30 2006-04-18 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US6417713B1 (en) * 1999-12-30 2002-07-09 Silicon Graphics, Inc. Programmable differential delay circuit with fine delay adjustment
DE10027703B4 (de) * 2000-06-03 2005-03-03 Sms Demag Ag Verfahren und Vorrichtung zum Umformen, insbesondere Fließpressen eines metallischen Werkstücks
DE10065376C1 (de) * 2000-12-27 2002-07-25 Infineon Technologies Ag Verzögerungsschaltung mit einstellbarer Verzögerung
US6696897B1 (en) * 2002-08-14 2004-02-24 Applied Microcircuits Corp. System and method for voltage controlled oscillator phase interpolation
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JP4775753B2 (ja) * 2004-08-03 2011-09-21 株式会社村田製作所 誘電体薄膜キャパシタの製造方法
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Also Published As

Publication number Publication date
JP3077813B2 (ja) 2000-08-21
DE69124002D1 (de) 1997-02-20
JPH0417410A (ja) 1992-01-22
EP0456231B1 (en) 1997-01-08
KR0153245B1 (ko) 1998-12-15
US5144174A (en) 1992-09-01
EP0456231A1 (en) 1991-11-13
DE69124002T2 (de) 1997-07-31

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