DE69124002D1 - Programmierbare Verzögerungsschaltung - Google Patents

Programmierbare Verzögerungsschaltung

Info

Publication number
DE69124002D1
DE69124002D1 DE69124002T DE69124002T DE69124002D1 DE 69124002 D1 DE69124002 D1 DE 69124002D1 DE 69124002 T DE69124002 T DE 69124002T DE 69124002 T DE69124002 T DE 69124002T DE 69124002 D1 DE69124002 D1 DE 69124002D1
Authority
DE
Germany
Prior art keywords
delay circuit
programmable delay
programmable
circuit
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69124002T
Other languages
English (en)
Other versions
DE69124002T2 (de
Inventor
Daisuke Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE69124002D1 publication Critical patent/DE69124002D1/de
Publication of DE69124002T2 publication Critical patent/DE69124002T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6257—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means
    • H03K17/6264—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means using current steering means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00182—Layout of the delay element using bipolar transistors using constant current sources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00228—Layout of the delay element having complementary input and output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
DE69124002T 1990-05-11 1991-05-08 Programmierbare Verzögerungsschaltung Expired - Lifetime DE69124002T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02119792A JP3077813B2 (ja) 1990-05-11 1990-05-11 プログラマブル遅延回路

Publications (2)

Publication Number Publication Date
DE69124002D1 true DE69124002D1 (de) 1997-02-20
DE69124002T2 DE69124002T2 (de) 1997-07-31

Family

ID=14770339

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124002T Expired - Lifetime DE69124002T2 (de) 1990-05-11 1991-05-08 Programmierbare Verzögerungsschaltung

Country Status (5)

Country Link
US (1) US5144174A (de)
EP (1) EP0456231B1 (de)
JP (1) JP3077813B2 (de)
KR (1) KR0153245B1 (de)
DE (1) DE69124002T2 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5144173A (en) * 1989-06-30 1992-09-01 Dallas Semiconductor Corporation Programmable delay line integrated circuit having programmable resistor circuit
EP0501827B1 (de) * 1991-03-01 1996-04-17 Kabushiki Kaisha Toshiba Multiplizierschaltung
US5327021A (en) * 1991-06-10 1994-07-05 Shinko Electric Ind., Co., Ltd. Waveform synthesizing circuit
JP2675455B2 (ja) * 1991-06-28 1997-11-12 三洋電機株式会社 可変遅延装置
JP3326619B2 (ja) * 1992-01-08 2002-09-24 ソニー株式会社 Ｐｗｍ回路
US5554950A (en) * 1992-02-04 1996-09-10 Brooktree Corporation Delay line providing an adjustable delay in response to binary input signals
FR2689339B1 (fr) * 1992-03-24 1996-12-13 Bull Sa Procede et dispositif de reglage de retard a plusieurs gammes.
US5347175A (en) * 1992-05-12 1994-09-13 The United States Of America As Represented By The Secretary Of Commerce Voltage comparator with reduced settling time
JP2595103Y2 (ja) * 1992-07-31 1999-05-24 安藤電気株式会社 差動ゲートによるタイミング調整回路
JP2595104Y2 (ja) * 1992-07-31 1999-05-24 安藤電気株式会社 差動ゲートによるタイミング調整回路
JP3550404B2 (ja) * 1992-09-10 2004-08-04 株式会社日立製作所 可変遅延回路及び可変遅延回路を用いたクロック信号供給装置
US5376849A (en) * 1992-12-04 1994-12-27 International Business Machines Corporation High resolution programmable pulse generator employing controllable delay
US5376833A (en) * 1992-12-11 1994-12-27 Texas Instruments Incorporated Current driver circuit
US5479091A (en) * 1992-12-11 1995-12-26 Texas Instruments Incorporated Output current reference circuit and method
ES2103106T3 (es) * 1993-02-25 1997-08-16 At & T Corp Linea de retardo variable de amplio margen y oscilador en anillo.
US5694070A (en) * 1994-07-11 1997-12-02 Vitesse Semiconductor Corporation Distributed ramp delay generator
US5631491A (en) * 1994-09-27 1997-05-20 Fuji Electric Co., Ltd. Lateral semiconductor device and method of fixing potential of the same
US5777501A (en) * 1996-04-29 1998-07-07 Mosaid Technologies Incorporated Digital delay line for a reduced jitter digital delay lock loop
US6054889A (en) * 1997-11-11 2000-04-25 Trw Inc. Mixer with improved linear range
US6480548B1 (en) 1997-11-17 2002-11-12 Silicon Graphics, Inc. Spacial derivative bus encoder and decoder
JP4146965B2 (ja) 1999-05-17 2008-09-10 株式会社アドバンテスト 遅延信号生成装置および半導体試験装置
US6775339B1 (en) 1999-08-27 2004-08-10 Silicon Graphics, Inc. Circuit design for high-speed digital communication
US6417713B1 (en) * 1999-12-30 2002-07-09 Silicon Graphics, Inc. Programmable differential delay circuit with fine delay adjustment
US7031420B1 (en) 1999-12-30 2006-04-18 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
DE10027703B4 (de) * 2000-06-03 2005-03-03 Sms Demag Ag Verfahren und Vorrichtung zum Umformen, insbesondere Fließpressen eines metallischen Werkstücks
DE10065376C1 (de) * 2000-12-27 2002-07-25 Infineon Technologies Ag Verzögerungsschaltung mit einstellbarer Verzögerung
US6696897B1 (en) * 2002-08-14 2004-02-24 Applied Microcircuits Corp. System and method for voltage controlled oscillator phase interpolation
US7446584B2 (en) * 2002-09-25 2008-11-04 Hrl Laboratories, Llc Time delay apparatus and method of using same
CN1951010A (zh) * 2003-10-10 2007-04-18 爱特梅尔股份有限公司 可选择延迟的脉冲发生器
JP4775753B2 (ja) * 2004-08-03 2011-09-21 株式会社村田製作所 誘電体薄膜キャパシタの製造方法
US7348821B2 (en) * 2004-09-22 2008-03-25 Intel Corporation Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors
US8054876B2 (en) * 2005-12-13 2011-11-08 Infinera Corporation Active delay line
US20090033389A1 (en) 2007-08-03 2009-02-05 Abadeer Wagdi W Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures
US7932552B2 (en) * 2007-08-03 2011-04-26 International Business Machines Corporation Multiple source-single drain field effect semiconductor device and circuit
US7814449B2 (en) * 2007-10-17 2010-10-12 International Business Machines Corporation Design structure for multiple source-single drain field effect semiconductor device and circuit
JP2011176392A (ja) * 2010-02-23 2011-09-08 Rohm Co Ltd 差動信号用マルチプレクサおよびパラレルシリアル変換器、それらを用いた信号処理回路、ディスプレイ装置
TWI513181B (zh) * 2013-04-23 2015-12-11 Sitronix Technology Corp Folding operation amplifier circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675562A (en) * 1983-08-01 1987-06-23 Fairchild Semiconductor Corporation Method and apparatus for dynamically controlling the timing of signals in automatic test systems
US4641048A (en) * 1984-08-24 1987-02-03 Tektronix, Inc. Digital integrated circuit propagation delay time controller
US4797586A (en) * 1987-11-25 1989-01-10 Tektronix, Inc. Controllable delay circuit
US4862020A (en) * 1988-06-20 1989-08-29 Tektronix, Inc. Electronic delay control circuit having pulse width maintenance

Also Published As

Publication number Publication date
JPH0417410A (ja) 1992-01-22
EP0456231A1 (de) 1991-11-13
KR910021020A (ko) 1991-12-20
KR0153245B1 (ko) 1998-12-15
DE69124002T2 (de) 1997-07-31
EP0456231B1 (de) 1997-01-08
US5144174A (en) 1992-09-01
JP3077813B2 (ja) 2000-08-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition