DE69133327D1 - Programmierbare logische Schaltung - Google Patents

Programmierbare logische Schaltung

Info

Publication number
DE69133327D1
DE69133327D1 DE69133327T DE69133327T DE69133327D1 DE 69133327 D1 DE69133327 D1 DE 69133327D1 DE 69133327 T DE69133327 T DE 69133327T DE 69133327 T DE69133327 T DE 69133327T DE 69133327 D1 DE69133327 D1 DE 69133327D1
Authority
DE
Germany
Prior art keywords
logic circuit
programmable logic
programmable
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69133327T
Other languages
English (en)
Other versions
DE69133327T2 (de
Inventor
Hung-Cheng Hsieh
William S Carter
Charles R Erickson
Edmond Y Cheung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE69133327D1 publication Critical patent/DE69133327D1/de
Publication of DE69133327T2 publication Critical patent/DE69133327T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
DE1991633327 1990-05-10 1991-05-08 Programmierbare logische Schaltung Expired - Lifetime DE69133327T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52233690A 1990-05-10 1990-05-10
US522336 2000-03-09

Publications (2)

Publication Number Publication Date
DE69133327D1 true DE69133327D1 (de) 2003-11-13
DE69133327T2 DE69133327T2 (de) 2004-08-05

Family

ID=24080466

Family Applications (2)

Application Number Title Priority Date Filing Date
DE1991632540 Expired - Lifetime DE69132540T2 (de) 1990-05-10 1991-05-08 Programmierbare logische Schaltung
DE1991633327 Expired - Lifetime DE69133327T2 (de) 1990-05-10 1991-05-08 Programmierbare logische Schaltung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE1991632540 Expired - Lifetime DE69132540T2 (de) 1990-05-10 1991-05-08 Programmierbare logische Schaltung

Country Status (4)

Country Link
EP (2) EP1046982B1 (de)
JP (1) JPH0766320B2 (de)
CA (1) CA2037142C (de)
DE (2) DE69132540T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5322812A (en) 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
US5633830A (en) * 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
USRE35977E (en) * 1992-05-08 1998-12-01 Altera Corporation Look up table implementation of fast carry arithmetic and exclusive-or operations
US5274581A (en) * 1992-05-08 1993-12-28 Altera Corporation Look up table implementation of fast carry for adders and counters
US5898319A (en) * 1993-09-02 1999-04-27 Xilinx, Inc. Method and structure for providing fast conditional sum in a field programmable gate array
US5546018A (en) * 1993-09-02 1996-08-13 Xilinx, Inc. Fast carry structure with synchronous input
US5629886A (en) * 1993-09-02 1997-05-13 Xilinx, Inc. Method and structure for providing fast propagation of a carry signal in a field programmable gate array
US6154053A (en) * 1993-09-02 2000-11-28 Xilinx, Inc. Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch
US6288570B1 (en) 1993-09-02 2001-09-11 Xilinx, Inc. Logic structure and circuit for fast carry
US5349250A (en) * 1993-09-02 1994-09-20 Xilinx, Inc. Logic structure and circuit for fast carry
GB2317248B (en) * 1996-09-02 2001-08-15 Siemens Plc Floating point number data processing means
US5966029A (en) * 1997-07-15 1999-10-12 Motorola, Inc. Multi-bit exclusive or
JP4852149B2 (ja) * 2007-05-21 2012-01-11 ルネサスエレクトロニクス株式会社 半導体装置
RU2503993C1 (ru) * 2012-04-26 2014-01-10 федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Пермский национальный исследовательский политехнический университет" Программируемое логическое устройство
RU2573732C2 (ru) * 2014-02-25 2016-01-27 Сергей Феофентович Тюрин Программируемое логическое устройство
RU2602780C2 (ru) * 2014-04-17 2016-11-20 Сергей Феофентович Тюрин Программируемое логическое устройство
RU2573758C2 (ru) * 2014-04-25 2016-01-27 Сергей Феофентович Тюрин Программируемое логическое устройство
RU2547229C1 (ru) * 2014-05-21 2015-04-10 федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Пермский национальный исследовательский политехнический университет" Программируемое логическое устройство
RU2544750C1 (ru) * 2014-05-22 2015-03-20 федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Пермский национальный исследовательский политехнический университет" Программируемое логическое устройство

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5841533B2 (ja) * 1975-10-31 1983-09-13 日本電気株式会社 ゼンカゲンサンカイロ
US4218747A (en) * 1978-06-05 1980-08-19 Fujitsu Limited Arithmetic and logic unit using basic cells
EP0098692A3 (de) * 1982-07-01 1986-04-16 Hewlett-Packard Company Einrichtung zur Addition von ersten und zweiten binären Operanden
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
JPS6270935A (ja) * 1985-09-24 1987-04-01 Sharp Corp デイジタル加算器
US4758745B1 (en) * 1986-09-19 1994-11-15 Actel Corp User programmable integrated circuit interconnect architecture and test method
JPH01180633A (ja) * 1988-01-12 1989-07-18 Mitsubishi Electric Corp 加算器
JPH01181127A (ja) * 1988-01-14 1989-07-19 Fujitsu Ltd 並列形全加算器
DE3850096D1 (de) * 1988-03-19 1994-07-14 Itt Ind Gmbh Deutsche CMOS-Parallel-Serien-Multiplizierschaltung sowie deren Multiplizier- und Addierstufen.

Also Published As

Publication number Publication date
EP0456475A2 (de) 1991-11-13
EP1046982B1 (de) 2003-10-08
EP0456475B1 (de) 2001-02-28
JPH04242825A (ja) 1992-08-31
EP1046982A2 (de) 2000-10-25
DE69132540T2 (de) 2001-07-05
EP0456475A3 (en) 1993-02-24
DE69133327T2 (de) 2004-08-05
DE69132540D1 (de) 2001-04-05
EP1046982A3 (de) 2000-11-02
CA2037142A1 (en) 1991-11-11
CA2037142C (en) 1996-05-07
JPH0766320B2 (ja) 1995-07-19

Similar Documents

Publication Publication Date Title
DE69122065D1 (de) Programmierbare integrierte Schaltung
DE69411292D1 (de) Programmierbare logische Schaltung
DE69124002D1 (de) Programmierbare Verzögerungsschaltung
DE68917235D1 (de) Programmierbare logische Schaltung.
DE69024638D1 (de) Aktivierungsschaltung
DE69231612D1 (de) Integrierte Schaltung mit programmierbarem Ausgang
DE69131531D1 (de) Integrierschaltung
DE69117553D1 (de) Ausgangsschaltung
DE69119152D1 (de) Schaltungsanordnung
DE69133327D1 (de) Programmierbare logische Schaltung
DE4291224T1 (de) BiCMOS-Logik-Verknüpfungsschaltung
BR9006653A (pt) Complexo central de circuitos eletronicos
DE69306131D1 (de) Komplementäre logische Schaltung
EP0488678A3 (en) Programmable integrated circuit
DE69128500D1 (de) Emittergekoppelte logische Schaltung
DE69027490D1 (de) Nichtflüchtige programmierbare Verbindungsschaltung
DE69026256D1 (de) Verschlüsselungsschaltung mit programmierbarer logik
DE69507425D1 (de) Programmierbare pull-up Pufferschaltung
DE69114547D1 (de) Sequentielle Logikschaltungsvorrichtung.
DE69118128D1 (de) Speiseschaltung
DE69227144D1 (de) Programmierbare logische Einheit
DE69129739D1 (de) Speicherschaltung
GB9103461D0 (en) Logic circuit
DE69126832D1 (de) BiCMOS logische Schaltung
DE69123167D1 (de) Bi-MOS-integrierte logische Schaltung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition