DE69227144D1 - Programmierbare logische Einheit - Google Patents

Programmierbare logische Einheit

Info

Publication number
DE69227144D1
DE69227144D1 DE69227144T DE69227144T DE69227144D1 DE 69227144 D1 DE69227144 D1 DE 69227144D1 DE 69227144 T DE69227144 T DE 69227144T DE 69227144 T DE69227144 T DE 69227144T DE 69227144 D1 DE69227144 D1 DE 69227144D1
Authority
DE
Germany
Prior art keywords
programmable logic
logic unit
unit
programmable
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69227144T
Other languages
English (en)
Other versions
DE69227144T2 (de
Inventor
Yukihiro Saeki
Hiroki Muroga
Tomohisa C O Intell Shigematsu
Toshio Hibi
Yasuo Kawahara
Kazunao Maru
Kenneth Austin
Gordon Stirling Work
Darren Martin Wedgwood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69227144D1 publication Critical patent/DE69227144D1/de
Publication of DE69227144T2 publication Critical patent/DE69227144T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
DE69227144T 1991-05-10 1992-05-07 Programmierbare logische Einheit Expired - Fee Related DE69227144T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10556791 1991-05-10

Publications (2)

Publication Number Publication Date
DE69227144D1 true DE69227144D1 (de) 1998-11-05
DE69227144T2 DE69227144T2 (de) 1999-03-18

Family

ID=14411112

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69227144T Expired - Fee Related DE69227144T2 (de) 1991-05-10 1992-05-07 Programmierbare logische Einheit

Country Status (4)

Country Link
US (1) US5309045A (de)
EP (1) EP0512536B1 (de)
KR (1) KR950012952B1 (de)
DE (1) DE69227144T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386155A (en) * 1993-03-30 1995-01-31 Intel Corporation Apparatus and method for selecting polarity and output type in a programmable logic device
US5652902A (en) * 1993-06-08 1997-07-29 Theseus Research, Inc. Asynchronous register for null convention logic systems
US5438295A (en) * 1993-06-11 1995-08-01 Altera Corporation Look-up table using multi-level decode
US5815024A (en) * 1993-06-11 1998-09-29 Altera Corporation Look-up table using multi-level decode
CA2126265A1 (en) * 1993-09-27 1995-03-28 Michael Robert Cantone System for synthesizing field programmable gate array implementations from high level circuit descriptions
US5737578A (en) * 1994-11-18 1998-04-07 International Business Machines Corp. Apparatus and method for partitioning multiport rams
US5646546A (en) * 1995-06-02 1997-07-08 International Business Machines Corporation Programmable logic cell having configurable gates and multiplexers
US5781032A (en) * 1996-09-09 1998-07-14 International Business Machines Corporation Programmable inverter circuit used in a programmable logic cell
JP5012816B2 (ja) * 2006-12-28 2012-08-29 日本電気株式会社 信号選択装置とシステムと回路エミュレータ及び方法並びにプログラム

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
GB2202356B (en) * 1985-02-27 1989-10-11 Xilinx Inc Configurable combinational logic circuit
US4684830A (en) * 1985-03-22 1987-08-04 Monolithic Memories, Inc. Output circuit for a programmable logic array
US4933577A (en) * 1985-03-22 1990-06-12 Advanced Micro Devices, Inc. Output circuit for a programmable logic array
US4742252A (en) * 1985-03-29 1988-05-03 Advanced Micro Devices, Inc. Multiple array customizable logic device
US4789951A (en) * 1986-05-16 1988-12-06 Advanced Micro Devices, Inc. Programmable array logic cell
US4910417A (en) * 1986-09-19 1990-03-20 Actel Corporation Universal logic module comprising multiplexers
US5019736A (en) * 1986-11-07 1991-05-28 Concurrent Logic, Inc. Programmable logic cell and array
DE3875909T2 (de) * 1987-11-20 1993-05-13 Kawasaki Steel Co Programmierbare logische vorrichtung.
US4878200A (en) * 1987-12-30 1989-10-31 Intel Corporation Product term sharing/allocation in an EPROM array
AU614426B2 (en) * 1988-08-31 1991-08-29 Fujitsu Limited Constitution for expanding logic scale of a programmable logic array
GB8828828D0 (en) * 1988-12-09 1989-01-18 Pilkington Micro Electronics Semiconductor integrated circuit
US4912345A (en) * 1988-12-29 1990-03-27 Sgs-Thomson Microelectronics, Inc. Programmable summing functions for programmable logic devices
US5027011A (en) * 1989-10-31 1991-06-25 Sgs-Thomson Microelectronics, Inc. Input row drivers for programmable logic devices
US5144166A (en) * 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array

Also Published As

Publication number Publication date
KR920022672A (ko) 1992-12-19
DE69227144T2 (de) 1999-03-18
EP0512536B1 (de) 1998-09-30
US5309045A (en) 1994-05-03
EP0512536A3 (de) 1995-08-02
EP0512536A2 (de) 1992-11-11
KR950012952B1 (ko) 1995-10-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee