DE69304471D1 - Programmierbare logische Vorrichtung - Google Patents
Programmierbare logische VorrichtungInfo
- Publication number
- DE69304471D1 DE69304471D1 DE69304471T DE69304471T DE69304471D1 DE 69304471 D1 DE69304471 D1 DE 69304471D1 DE 69304471 T DE69304471 T DE 69304471T DE 69304471 T DE69304471 T DE 69304471T DE 69304471 D1 DE69304471 D1 DE 69304471D1
- Authority
- DE
- Germany
- Prior art keywords
- programmable logic
- logic device
- programmable
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US92426792A | 1992-08-03 | 1992-08-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69304471D1 true DE69304471D1 (de) | 1996-10-10 |
DE69304471T2 DE69304471T2 (de) | 1997-03-20 |
Family
ID=25449983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69304471T Expired - Fee Related DE69304471T2 (de) | 1992-08-03 | 1993-06-28 | Programmierbare logische Vorrichtung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5617042A (de) |
EP (1) | EP0584910B1 (de) |
JP (1) | JP3325662B2 (de) |
KR (1) | KR940004460A (de) |
DE (1) | DE69304471T2 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5198705A (en) | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
US5689686A (en) * | 1994-07-29 | 1997-11-18 | Cypress Semiconductor Corp. | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability |
US6570404B1 (en) | 1996-03-29 | 2003-05-27 | Altera Corporation | High-performance programmable logic architecture |
US6526461B1 (en) * | 1996-07-18 | 2003-02-25 | Altera Corporation | Interconnect chip for programmable logic devices |
US6229812B1 (en) * | 1996-10-28 | 2001-05-08 | Paxonet Communications, Inc. | Scheduling techniques for data cells in a data switch |
US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
US5936426A (en) | 1997-02-03 | 1999-08-10 | Actel Corporation | Logic function module for field programmable array |
US6150837A (en) | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6034541A (en) * | 1997-04-07 | 2000-03-07 | Lattice Semiconductor Corporation | In-system programmable interconnect circuit |
US6289494B1 (en) | 1997-11-12 | 2001-09-11 | Quickturn Design Systems, Inc. | Optimized emulation and prototyping architecture |
US6045816A (en) * | 1998-06-17 | 2000-04-04 | Isp Investments Inc. | Water-based microemulsion of a pyrethroid |
US6243664B1 (en) | 1998-10-27 | 2001-06-05 | Cypress Semiconductor Corporation | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability |
US7426665B1 (en) | 2000-09-02 | 2008-09-16 | Actel Corporation | Tileable field-programmable gate array architecture |
US6937063B1 (en) | 2000-09-02 | 2005-08-30 | Actel Corporation | Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array |
US7015719B1 (en) * | 2000-09-02 | 2006-03-21 | Actel Corporation | Tileable field-programmable gate array architecture |
US6870396B2 (en) * | 2000-09-02 | 2005-03-22 | Actel Corporation | Tileable field-programmable gate array architecture |
US6476636B1 (en) * | 2000-09-02 | 2002-11-05 | Actel Corporation | Tileable field-programmable gate array architecture |
US7454664B2 (en) * | 2003-06-30 | 2008-11-18 | International Business Machines Corporation | JTAGchain bus switching and configuring device |
US10284185B1 (en) * | 2017-12-18 | 2019-05-07 | Xilinx, Inc. | Selectively providing clock signals using a programmable control circuit |
TW202117932A (zh) * | 2019-10-15 | 2021-05-01 | 瑞昱半導體股份有限公司 | 積體電路及動態腳位控制方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5015884A (en) * | 1985-03-29 | 1991-05-14 | Advanced Micro Devices, Inc. | Multiple array high performance programmable logic device family |
US4758746A (en) * | 1985-08-12 | 1988-07-19 | Monolithic Memories, Inc. | Programmable logic array with added array of gates and added output routing flexibility |
US4771285A (en) * | 1985-11-05 | 1988-09-13 | Advanced Micro Devices, Inc. | Programmable logic cell with flexible clocking and flexible feedback |
US4789951A (en) * | 1986-05-16 | 1988-12-06 | Advanced Micro Devices, Inc. | Programmable array logic cell |
US5229214A (en) * | 1989-07-31 | 1993-07-20 | Akzo N.V. | Preprimed metal substrates for formed metal applications |
US5191243A (en) * | 1991-05-06 | 1993-03-02 | Lattice Semiconductor Corporation | Output logic macrocell with enhanced functional capabilities |
US5130574A (en) * | 1991-05-06 | 1992-07-14 | Lattice Semiconductor Corporation | Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device |
US5204556A (en) * | 1991-05-06 | 1993-04-20 | Lattice Semiconductor Corporation | Programmable interconnect structure for logic blocks |
US5260610A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic element interconnections for programmable logic array integrated circuits |
US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US5258668A (en) * | 1992-05-08 | 1993-11-02 | Altera Corporation | Programmable logic array integrated circuits with cascade connections between logic modules |
-
1993
- 1993-06-28 DE DE69304471T patent/DE69304471T2/de not_active Expired - Fee Related
- 1993-06-28 EP EP93305041A patent/EP0584910B1/de not_active Expired - Lifetime
- 1993-08-02 JP JP19136193A patent/JP3325662B2/ja not_active Expired - Fee Related
- 1993-08-03 KR KR1019930015072A patent/KR940004460A/ko not_active Application Discontinuation
-
1995
- 1995-06-07 US US08/483,623 patent/US5617042A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0584910A1 (de) | 1994-03-02 |
JPH06188725A (ja) | 1994-07-08 |
US5617042A (en) | 1997-04-01 |
EP0584910B1 (de) | 1996-09-04 |
DE69304471T2 (de) | 1997-03-20 |
JP3325662B2 (ja) | 2002-09-17 |
KR940004460A (ko) | 1994-03-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: VANTIS CORP.)N.D.GES.D.STAATES DELAWARE), SUNNYVAL |
|
8339 | Ceased/non-payment of the annual fee |