DE69126832D1 - BiCMOS logische Schaltung - Google Patents

BiCMOS logische Schaltung

Info

Publication number
DE69126832D1
DE69126832D1 DE69126832T DE69126832T DE69126832D1 DE 69126832 D1 DE69126832 D1 DE 69126832D1 DE 69126832 T DE69126832 T DE 69126832T DE 69126832 T DE69126832 T DE 69126832T DE 69126832 D1 DE69126832 D1 DE 69126832D1
Authority
DE
Germany
Prior art keywords
logic circuit
bicmos logic
bicmos
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126832T
Other languages
English (en)
Other versions
DE69126832T2 (de
Inventor
Koichiro Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP22869190A external-priority patent/JPH04109666A/ja
Priority claimed from JP02228687A external-priority patent/JP3099351B2/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69126832D1 publication Critical patent/DE69126832D1/de
Application granted granted Critical
Publication of DE69126832T2 publication Critical patent/DE69126832T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
DE69126832T 1990-08-29 1991-08-28 BiCMOS logische Schaltung Expired - Fee Related DE69126832T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP22869190A JPH04109666A (ja) 1990-08-29 1990-08-29 ＢｉＣＭＯＳ論理回路
JP02228687A JP3099351B2 (ja) 1990-08-29 1990-08-29 ＢｉＣＭＯＳ論理回路

Publications (2)

Publication Number Publication Date
DE69126832D1 true DE69126832D1 (de) 1997-08-21
DE69126832T2 DE69126832T2 (de) 1997-11-20

Family

ID=26528406

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69126832T Expired - Fee Related DE69126832T2 (de) 1990-08-29 1991-08-28 BiCMOS logische Schaltung

Country Status (3)

Country Link
US (1) US5159214A (de)
EP (1) EP0473409B1 (de)
DE (1) DE69126832T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05198755A (ja) * 1991-08-29 1993-08-06 Mitsubishi Electric Corp 半導体論理回路
JP2734254B2 (ja) * 1991-10-15 1998-03-30 日本電気株式会社 レベル変換回路
US5331593A (en) * 1993-03-03 1994-07-19 Micron Semiconductor, Inc. Read circuit for accessing dynamic random access memories (DRAMS)
JP3441152B2 (ja) * 1994-04-15 2003-08-25 株式会社東芝 ＢｉＣＭＯＳ回路
JP2647014B2 (ja) * 1994-09-08 1997-08-27 日本電気株式会社 ＢｉＣＭＯＳ論理回路
JP3633061B2 (ja) * 1995-10-19 2005-03-30 三菱電機株式会社 半導体集積回路装置
US6307404B1 (en) * 1999-04-28 2001-10-23 Analog Devices, Inc. Gate structures with reduced propagation-delay variations
TW201026159A (en) * 2008-12-26 2010-07-01 Vanguard Int Semiconduct Corp Electrostatic discharge protection circuit and integrated circuit utilizing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0693626B2 (ja) * 1983-07-25 1994-11-16 株式会社日立製作所 半導体集積回路装置
JPS60125015A (ja) * 1983-12-12 1985-07-04 Hitachi Ltd インバ−タ回路
US4616146A (en) * 1984-09-04 1986-10-07 Motorola, Inc. BI-CMOS driver circuit
US4649295A (en) * 1986-01-13 1987-03-10 Motorola, Inc. BIMOS logic gate
JPS62221219A (ja) * 1986-03-22 1987-09-29 Toshiba Corp 論理回路
JPS6382122A (ja) * 1986-09-26 1988-04-12 Toshiba Corp 論理回路
JPH02214219A (ja) * 1989-02-14 1990-08-27 Nec Corp バイポーラｍｏｓ３値出力バッファ
JP2865256B2 (ja) * 1989-03-02 1999-03-08 株式会社日立製作所 バイポーラ・ｍｏｓ論理回路

Also Published As

Publication number Publication date
US5159214A (en) 1992-10-27
EP0473409B1 (de) 1997-07-16
EP0473409A2 (de) 1992-03-04
EP0473409A3 (en) 1992-07-01
DE69126832T2 (de) 1997-11-20

Similar Documents

Publication Publication Date Title
FI901893A0 (fi) Kopplingsanordning.
DE69128566D1 (de) Zusammengesetzte integrierte Schaltungsanordnung
DE4291224T1 (de) BiCMOS-Logik-Verknüpfungsschaltung
DE69117553T2 (de) Ausgangsschaltung
DE69119152D1 (de) Schaltungsanordnung
DE487874T1 (de) Signalgestalter.
KR950700635A (ko) BiCMOS 논리회로(BiCMOS LOGIC CIRCUIT)
DE69122463T2 (de) Integrierte Schaltkreise
DE69132540T2 (de) Programmierbare logische Schaltung
DE69306131T2 (de) Komplementäre logische Schaltung
DE69128500D1 (de) Emittergekoppelte logische Schaltung
DE68925856D1 (de) Logische Bicmos-Schaltung
DE69031846D1 (de) Integrierte BICMOS-Schaltung
FR2630601B1 (fr) Circuit inverseur bicmos
DE69126832D1 (de) BiCMOS logische Schaltung
DE69123167T2 (de) Bi-MOS-integrierte logische Schaltung
DE69429409D1 (de) BICMOS-Logikschaltung
DE68916249T2 (de) Logikschaltung.
DE69122184D1 (de) Schwellenfreie logische Schaltung
DE59009666D1 (de) Schaltungsanordnung.
ATA185892A (de) Integrierte bicmos-schaltungsanordnung
KR920001365U (ko) 고속탐색회로
DE59009022D1 (de) Integrierte Flip-Flop-Schaltung.
KR930012326U (ko) 씨모스 논리회로
KR910020871U (ko) 블랭크-스킵회로

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee