DE69122463T2 - Integrierte Schaltkreise - Google Patents

Integrierte Schaltkreise

Info

Publication number
DE69122463T2
DE69122463T2 DE69122463T DE69122463T DE69122463T2 DE 69122463 T2 DE69122463 T2 DE 69122463T2 DE 69122463 T DE69122463 T DE 69122463T DE 69122463 T DE69122463 T DE 69122463T DE 69122463 T2 DE69122463 T2 DE 69122463T2
Authority
DE
Germany
Prior art keywords
integrated circuits
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69122463T
Other languages
English (en)
Other versions
DE69122463D1 (de
Inventor
Paolo Tabacco
Carol A Price
Hugh P Mcadams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69122463D1 publication Critical patent/DE69122463D1/de
Application granted granted Critical
Publication of DE69122463T2 publication Critical patent/DE69122463T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69122463T 1990-07-31 1991-07-31 Integrierte Schaltkreise Expired - Fee Related DE69122463T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/560,541 US5191555A (en) 1990-07-31 1990-07-31 Cmos single input buffer for multiplexed inputs

Publications (2)

Publication Number Publication Date
DE69122463D1 DE69122463D1 (de) 1996-11-07
DE69122463T2 true DE69122463T2 (de) 1997-02-20

Family

ID=24238239

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69122463T Expired - Fee Related DE69122463T2 (de) 1990-07-31 1991-07-31 Integrierte Schaltkreise

Country Status (3)

Country Link
US (1) US5191555A (de)
EP (1) EP0475057B1 (de)
DE (1) DE69122463T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0554654A (ja) * 1991-08-27 1993-03-05 Nec Corp ダイナミツクｒａｍ
KR930008838A (ko) * 1991-10-31 1993-05-22 김광호 어드레스 입력 버퍼
US5264741A (en) * 1992-06-19 1993-11-23 Aptix Corporation Low current, fast, CMOS static pullup circuit for static random-access memories
KR0120592B1 (ko) * 1994-09-09 1997-10-20 김주용 신호 변환 장치를 갖고 있는 어드레스 입력버퍼
US5670907A (en) * 1995-03-14 1997-09-23 Lattice Semiconductor Corporation VBB reference for pumped substrates
KR0145852B1 (ko) * 1995-04-14 1998-11-02 김광호 반도체메모리소자의 어드레스버퍼
US5635861A (en) * 1995-05-23 1997-06-03 International Business Machines Corporation Off chip driver circuit
US5744944A (en) 1995-12-13 1998-04-28 Sgs-Thomson Microelectronics, Inc. Programmable bandwidth voltage regulator
US5883838A (en) * 1996-01-19 1999-03-16 Stmicroelectronics, Inc. Device and method for driving a conductive path with a signal
US5999019A (en) * 1997-10-10 1999-12-07 The Research Foundation Of State University Of New York Fast CMOS logic circuit with critical voltage transition logic
US5986471A (en) * 1997-10-15 1999-11-16 Lucent Technologies Inc. Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices
US6341135B1 (en) * 1998-02-26 2002-01-22 3Com Corporation Low power buffer system for network communications
US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
JP2002124637A (ja) 2000-10-18 2002-04-26 Oki Micro Design Co Ltd 半導体集積回路
US7564268B2 (en) * 2006-11-07 2009-07-21 Integrated Device Technology, Inc Low power logic output buffer
US8254178B2 (en) * 2007-08-27 2012-08-28 Infineon Technologies Ag Self-timed integrating differential current
TWI360880B (en) * 2008-06-10 2012-03-21 Promos Technologies Inc Leakage test method for dynamic random access memo
US20120210438A1 (en) * 2011-02-15 2012-08-16 Guobiao Zhang Secure Three-Dimensional Mask-Programmed Read-Only Memory
US11575254B2 (en) * 2019-11-19 2023-02-07 Stmicroelectronics International N.V. Overvoltage protection circuit for a PMOS based switch

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541078A (en) * 1982-12-22 1985-09-10 At&T Bell Laboratories Memory using multiplexed row and column address lines
JPH0787034B2 (ja) * 1984-05-07 1995-09-20 株式会社日立製作所 半導体集積回路装置
US4661930A (en) * 1984-08-02 1987-04-28 Texas Instruments Incorporated High speed testing of integrated circuit
US4636986B1 (en) * 1985-01-22 1999-12-07 Texas Instruments Inc Separately addressable memory arrays in a multiple array semiconductor chip

Also Published As

Publication number Publication date
EP0475057A1 (de) 1992-03-18
EP0475057B1 (de) 1996-10-02
DE69122463D1 (de) 1996-11-07
US5191555A (en) 1993-03-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee