DE69123167D1 - Bi-MOS-integrierte logische Schaltung - Google Patents

Bi-MOS-integrierte logische Schaltung

Info

Publication number
DE69123167D1
DE69123167D1 DE69123167T DE69123167T DE69123167D1 DE 69123167 D1 DE69123167 D1 DE 69123167D1 DE 69123167 T DE69123167 T DE 69123167T DE 69123167 T DE69123167 T DE 69123167T DE 69123167 D1 DE69123167 D1 DE 69123167D1
Authority
DE
Germany
Prior art keywords
logic circuit
integrated logic
mos integrated
mos
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69123167T
Other languages
English (en)
Other versions
DE69123167T2 (de
Inventor
Hiroyuki Hara
Yasuhiro Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69123167D1 publication Critical patent/DE69123167D1/de
Application granted granted Critical
Publication of DE69123167T2 publication Critical patent/DE69123167T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
DE69123167T 1990-04-20 1991-04-18 Bi-MOS-integrierte logische Schaltung Expired - Fee Related DE69123167T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2104579A JPH043619A (ja) 1990-04-20 1990-04-20 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69123167D1 true DE69123167D1 (de) 1997-01-02
DE69123167T2 DE69123167T2 (de) 1997-04-10

Family

ID=14384348

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69123167T Expired - Fee Related DE69123167T2 (de) 1990-04-20 1991-04-18 Bi-MOS-integrierte logische Schaltung

Country Status (5)

Country Link
US (1) US5126595A (de)
EP (1) EP0452919B1 (de)
JP (1) JPH043619A (de)
KR (1) KR940007299B1 (de)
DE (1) DE69123167T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430408A (en) * 1993-03-08 1995-07-04 Texas Instruments Incorporated Transmission gate circuit
USRE38398E1 (en) 1996-02-14 2004-01-27 L'oreal S.A. Case for a cosmetic care product with a flexible bottom
FR2744602B1 (fr) * 1996-02-14 1998-03-06 Oreal Boitier notamment de maquillage et/ou de soin a fond souple
EP0828281A4 (de) * 1996-03-06 1999-09-01 Toshiba Kk Kathodenstrahlröhre und herstellungsverfahren derselben
JP3485092B2 (ja) * 2001-01-19 2004-01-13 セイコーエプソン株式会社 半導体装置およびその製造方法
JP2006061189A (ja) * 2004-08-24 2006-03-09 Key Tranding Co Ltd 化粧料容器
CN103490766A (zh) * 2013-08-29 2014-01-01 苏州苏尔达信息科技有限公司 一种高速高精度源极跟随电路
KR101805162B1 (ko) * 2017-04-17 2017-12-05 충남대학교산학협력단 수분 저항성 및 내구성이 우수한 유기성 고밀도 제재 및 이의 제조방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783252B2 (ja) * 1982-07-12 1995-09-06 株式会社日立製作所 半導体集積回路装置
KR910008521B1 (ko) * 1983-01-31 1991-10-18 가부시기가이샤 히다찌세이사꾸쇼 반도체집적회로
JPS60125015A (ja) * 1983-12-12 1985-07-04 Hitachi Ltd インバ−タ回路
JPH07107973B2 (ja) * 1984-03-26 1995-11-15 株式会社日立製作所 スイツチング回路
US4703203A (en) * 1986-10-03 1987-10-27 Motorola, Inc. BICMOS logic having three state output
US4912347A (en) * 1987-08-25 1990-03-27 American Telephone And Telegraph Company, At&T Bell Laboratories CMOS to ECL output buffer
JPS6468021A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Logic circuit
JP2693501B2 (ja) * 1988-07-29 1997-12-24 株式会社東芝 差動増幅回路
JP2696991B2 (ja) * 1988-09-26 1998-01-14 日本電気株式会社 ＢｉＣＭＯＳ論理回路
JPH03136365A (ja) * 1989-10-23 1991-06-11 Oki Electric Ind Co Ltd バイポーラｍｉｓ複合半導体装置
JPH03280713A (ja) * 1990-03-29 1991-12-11 Nec Corp ＢｉＣＭＯＳ論理ゲート回路

Also Published As

Publication number Publication date
KR940007299B1 (ko) 1994-08-12
KR910019340A (ko) 1991-11-30
EP0452919A3 (en) 1991-11-13
EP0452919A2 (de) 1991-10-23
EP0452919B1 (de) 1996-11-20
DE69123167T2 (de) 1997-04-10
JPH043619A (ja) 1992-01-08
US5126595A (en) 1992-06-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee