DE68913951D1 - Verzögerungsschaltung. - Google Patents

Verzögerungsschaltung.

Info

Publication number
DE68913951D1
DE68913951D1 DE89123609T DE68913951T DE68913951D1 DE 68913951 D1 DE68913951 D1 DE 68913951D1 DE 89123609 T DE89123609 T DE 89123609T DE 68913951 T DE68913951 T DE 68913951T DE 68913951 D1 DE68913951 D1 DE 68913951D1
Authority
DE
Germany
Prior art keywords
delay circuit
delay
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89123609T
Other languages
English (en)
Other versions
DE68913951T2 (de
Inventor
Charles K Erdelyi
Mark G Marshall
John W Mathews
Patrick E Perry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE68913951D1 publication Critical patent/DE68913951D1/de
Publication of DE68913951T2 publication Critical patent/DE68913951T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
DE68913951T 1989-02-13 1989-12-21 Verzögerungsschaltung. Expired - Fee Related DE68913951T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/309,530 US5059837A (en) 1989-02-13 1989-02-13 Data dependent variable time delay circuit

Publications (2)

Publication Number Publication Date
DE68913951D1 true DE68913951D1 (de) 1994-04-21
DE68913951T2 DE68913951T2 (de) 1994-09-22

Family

ID=23198601

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68913951T Expired - Fee Related DE68913951T2 (de) 1989-02-13 1989-12-21 Verzögerungsschaltung.

Country Status (4)

Country Link
US (1) US5059837A (de)
EP (1) EP0382938B1 (de)
JP (1) JP2620391B2 (de)
DE (1) DE68913951T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563525A (ja) * 1991-08-29 1993-03-12 Nec Corp パルス幅可変回路
JP3247128B2 (ja) * 1991-10-09 2002-01-15 富士通株式会社 可変遅延回路
JPH08125509A (ja) * 1994-10-25 1996-05-17 Mitsubishi Electric Corp 可変遅延回路、リング発振器、及びフリップフロップ回路

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2964708A (en) * 1955-11-17 1960-12-13 Digital Control Systems Inc Time interval generating circuits
US3102208A (en) * 1960-02-17 1963-08-27 Honeywell Regulator Co Race-preventing flip-flop switches by trailing edge of clock pulse applied through charged series capacitor
US3346746A (en) * 1965-10-20 1967-10-10 Bell Telephone Labor Inc Monostable multivibrator circuit having variable timing interval
US3558924A (en) * 1967-10-23 1971-01-26 Gen Precision Systems Inc Master timing circuit for providing different time delays to different systems
US3675133A (en) * 1971-06-21 1972-07-04 Ibm Apparatus and method independently varying the widths of a plurality of pulses
US3753012A (en) * 1972-02-17 1973-08-14 Motorola Inc Circuit for providing precise time delay
US4140927A (en) * 1977-04-04 1979-02-20 Teletype Corporation Non-overlapping clock generator
JPS5685934A (en) * 1979-12-14 1981-07-13 Nippon Telegr & Teleph Corp <Ntt> Control signal generating circuit
DE3072118D1 (en) * 1979-12-26 1988-09-22 Toshiba Kk A driver circuit for charge coupled device
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device
JPS5799029A (en) * 1980-12-12 1982-06-19 Citizen Watch Co Ltd Input device for electronic watch
JPS57131126A (en) * 1981-02-05 1982-08-13 Sanyo Electric Co Ltd Operation time setting device
US4423339A (en) * 1981-02-23 1983-12-27 Motorola, Inc. Majority logic gate
IT1210945B (it) * 1982-10-22 1989-09-29 Ates Componenti Elettron Circuito di interfaccia per generatori di segnali di sincronismo a due fasi nonsovrapposte.
JPS6033732A (ja) * 1983-08-04 1985-02-21 Nec Corp 遅延回路
JPS6152022A (ja) * 1984-08-22 1986-03-14 Hitachi Ltd 半導体集積回路装置
US4638188A (en) * 1984-08-27 1987-01-20 Cray Research, Inc. Phase modulated pulse logic for gallium arsenide
US4641046A (en) * 1985-06-17 1987-02-03 Signetics Corporation NOR gate with logical low output clamp
JPS63193606A (ja) * 1987-02-04 1988-08-10 Nec Corp パルス調整回路
JPS63226110A (ja) * 1987-03-16 1988-09-20 Fujitsu Ltd ヒステリシスインバ−タ回路
US5111085A (en) * 1987-04-29 1992-05-05 Ncr Corporation Digitally controlled delay circuit
US4896059A (en) * 1988-07-26 1990-01-23 Microelectronics Center Of North Carolina Circuit to perform variable threshold logic

Also Published As

Publication number Publication date
US5059837A (en) 1991-10-22
EP0382938A1 (de) 1990-08-22
DE68913951T2 (de) 1994-09-22
JPH02241109A (ja) 1990-09-25
EP0382938B1 (de) 1994-03-16
JP2620391B2 (ja) 1997-06-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee