DE69308978D1 - Verzögerungsschaltung - Google Patents

Verzögerungsschaltung

Info

Publication number
DE69308978D1
DE69308978D1 DE69308978T DE69308978T DE69308978D1 DE 69308978 D1 DE69308978 D1 DE 69308978D1 DE 69308978 T DE69308978 T DE 69308978T DE 69308978 T DE69308978 T DE 69308978T DE 69308978 D1 DE69308978 D1 DE 69308978D1
Authority
DE
Germany
Prior art keywords
delay circuit
delay
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69308978T
Other languages
English (en)
Other versions
DE69308978T2 (de
Inventor
Jean-Luc Rainard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Application granted granted Critical
Publication of DE69308978D1 publication Critical patent/DE69308978D1/de
Publication of DE69308978T2 publication Critical patent/DE69308978T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032—Dc control of switching transistors
    • H03K2005/00039—Dc control of switching transistors having four transistors serially
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
DE69308978T 1992-09-22 1993-09-20 Verzögerungsschaltung Expired - Fee Related DE69308978T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9211267A FR2696061B1 (fr) 1992-09-22 1992-09-22 Procédé pour retarder temporellement un signal et circuit à retard correspondant.

Publications (2)

Publication Number Publication Date
DE69308978D1 true DE69308978D1 (de) 1997-04-24
DE69308978T2 DE69308978T2 (de) 1997-09-04

Family

ID=9433745

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69308978T Expired - Fee Related DE69308978T2 (de) 1992-09-22 1993-09-20 Verzögerungsschaltung

Country Status (5)

Country Link
US (1) US5416436A (de)
EP (1) EP0589763B1 (de)
JP (1) JPH06204791A (de)
DE (1) DE69308978T2 (de)
FR (1) FR2696061B1 (de)

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DE19501707C1 (de) * 1995-01-20 1996-06-05 Texas Instruments Deutschland Elektrisches Bauelement und Verfahren zum Abgleichen der inneren Laufzeit eines solchen elektrischen Bauelements
US5644262A (en) * 1995-02-24 1997-07-01 Intel Corporation Digitally controlled capacitive load
JP3862306B2 (ja) * 1995-06-23 2006-12-27 三菱電機株式会社 半導体装置
US5714907A (en) * 1996-07-29 1998-02-03 Intel Corporation Apparatus for providing digitally-adjustable floating MOS capacitance
JPH1049561A (ja) * 1996-08-07 1998-02-20 Mitsubishi Electric Corp 信号遅延計算方法
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
CA2224767A1 (en) * 1996-12-31 1998-06-30 Huang Chaogang Variable cmos vernier delay
JP3338758B2 (ja) * 1997-02-06 2002-10-28 日本電気株式会社 遅延回路
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5920518A (en) * 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US5774403A (en) * 1997-06-12 1998-06-30 Hewlett-Packard PVT self aligning internal delay line and method of operation
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
JP3560780B2 (ja) * 1997-07-29 2004-09-02 富士通株式会社 可変遅延回路及び半導体集積回路装置
US6201412B1 (en) * 1997-07-30 2001-03-13 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit with driver stabilization using parasitic capacitance
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US5926047A (en) 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US6101197A (en) 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
KR100271633B1 (ko) * 1997-11-01 2000-11-15 김영환 지연회로
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
JP2000138866A (ja) * 1998-10-30 2000-05-16 Nec Corp 電荷結合素子の信号処理装置
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
DE10005620A1 (de) 2000-02-09 2001-08-30 Infineon Technologies Ag Schaltungsanordnung
JP2001307480A (ja) * 2000-04-24 2001-11-02 Mitsubishi Electric Corp 半導体集積回路装置
JP2002076855A (ja) * 2000-08-29 2002-03-15 Advantest Corp 遅延回路、試験装置、コンデンサ
DE10164822B4 (de) * 2000-08-29 2007-04-12 Advantest Corp. Prüfvorrichtung
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6628154B2 (en) 2001-07-31 2003-09-30 Cypress Semiconductor Corp. Digitally controlled analog delay locked loop (DLL)
US20030048123A1 (en) * 2001-08-29 2003-03-13 Sun Microsystems, Inc. Integrated circuit and method of adjusting capacitance of a node of an integrated circuit
US6614275B1 (en) * 2002-04-04 2003-09-02 Sun Microsystems, Inc. Adjustable capacitances for DLL loop and power supply noise filters
KR100482370B1 (ko) * 2002-09-27 2005-04-13 삼성전자주식회사 게이트 산화막의 두께가 다른 반도체장치
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7425857B2 (en) * 2004-02-10 2008-09-16 Stmicroelectronics S.R.L. Time-delay circuit
DE602004006597D1 (de) * 2004-02-18 2007-07-05 St Microelectronics Srl Taktimpulsgenerator
TWI358902B (en) * 2007-12-31 2012-02-21 Ind Tech Res Inst Signal delay circuit
US8837229B1 (en) * 2013-03-15 2014-09-16 Synopsys, Inc. Circuit for generating negative bitline voltage
US9698760B1 (en) * 2014-01-31 2017-07-04 Marvell International Ltd. Continuous-time analog delay device
US9705484B2 (en) * 2015-06-25 2017-07-11 Mediatek Inc. Delay cell in a standard cell library

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016511A (en) * 1975-12-19 1977-04-05 The United States Of America As Represented By The Secretary Of The Air Force Programmable variable length high speed digital delay line
DE3165323D1 (en) * 1981-03-06 1984-09-13 Itt Ind Gmbh Deutsche Delay circuit with integrated insulated-layer field-effect transistor for digital signals, and application of the same to colour television receivers
JPS6089773A (ja) * 1983-08-01 1985-05-20 フエアチアイルド　カメラ　アンド　インストルメント　コ−ポレ−シヨン 自動テスト方式における信号のタイミングを動的に制御する方法及び装置
EP0439203A3 (de) * 1986-06-16 1991-08-28 Tektronix Inc. Schaltung mit veränderlicher Verzögerung
US5081380A (en) * 1989-10-16 1992-01-14 Advanced Micro Devices, Inc. Temperature self-compensated time delay circuits
JP3019340B2 (ja) * 1989-12-05 2000-03-13 セイコーエプソン株式会社 可変容量装置
KR930006228B1 (ko) * 1990-07-20 1993-07-09 삼성전자 주식회사 신호지연회로
FR2666183B1 (fr) * 1990-08-23 1992-11-06 Bull Sa Circuit a constante de temps reglable et application a un circuit a retard reglable.
EP0539831B1 (de) * 1991-11-01 1998-06-03 Hewlett-Packard Company Programmierbares Kapazitätsverzögerungselement in Pseudo-NMOS-Technik

Also Published As

Publication number Publication date
EP0589763A1 (de) 1994-03-30
JPH06204791A (ja) 1994-07-22
DE69308978T2 (de) 1997-09-04
EP0589763B1 (de) 1997-03-19
US5416436A (en) 1995-05-16
FR2696061B1 (fr) 1994-12-02
FR2696061A1 (fr) 1994-03-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee