DE69427339D1 - Begrenzungsschaltung - Google Patents
BegrenzungsschaltungInfo
- Publication number
- DE69427339D1 DE69427339D1 DE69427339T DE69427339T DE69427339D1 DE 69427339 D1 DE69427339 D1 DE 69427339D1 DE 69427339 T DE69427339 T DE 69427339T DE 69427339 T DE69427339 T DE 69427339T DE 69427339 D1 DE69427339 D1 DE 69427339D1
- Authority
- DE
- Germany
- Prior art keywords
- limiting circuit
- limiting
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5346988A JP2591463B2 (ja) | 1993-12-27 | 1993-12-27 | リミッタ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69427339D1 true DE69427339D1 (de) | 2001-07-05 |
DE69427339T2 DE69427339T2 (de) | 2001-09-27 |
Family
ID=18387173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69427339T Expired - Fee Related DE69427339T2 (de) | 1993-12-27 | 1994-12-21 | Begrenzerschaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5504697A (de) |
EP (1) | EP0660226B1 (de) |
JP (1) | JP2591463B2 (de) |
DE (1) | DE69427339T2 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5801977A (en) * | 1995-01-17 | 1998-09-01 | Hewlett-Packard Company | System and method for clipping integers |
GB2300054A (en) * | 1995-01-17 | 1996-10-23 | Hewlett Packard Co | Clipping integers |
US5764548A (en) * | 1995-09-29 | 1998-06-09 | Intel Corporation | Fast floating-point to integer conversion |
JPH0997178A (ja) * | 1995-09-29 | 1997-04-08 | Matsushita Electric Ind Co Ltd | 飽和演算処理装置および方法 |
EP0806722A1 (de) * | 1996-05-06 | 1997-11-12 | Motorola, Inc. | Verfahren und Vorrichtung für eine Multiplizier- und Akkumulierschaltung mit einem dynamischen Sättigungsbereich |
US5742533A (en) * | 1996-05-21 | 1998-04-21 | International Business Machines Corporation | Method and apparatus for modulus error checking |
EP0845741B1 (de) | 1996-11-29 | 2003-04-16 | Matsushita Electric Industrial Co., Ltd. | Prozessor mit verbessertem Rundungsprozess |
US5887181A (en) * | 1997-06-23 | 1999-03-23 | Sun Microsystems, Inc. | Method and apparatus for reducing a computational result to the range boundaries of an unsigned 8-bit integer in case of overflow |
KR100253407B1 (ko) * | 1998-01-23 | 2000-04-15 | 김영환 | 에프오디 회로 |
US6957238B1 (en) * | 2001-02-23 | 2005-10-18 | Altera Corporation | Method and system for deterministic pseudo-random valid entry resolution |
US7461118B2 (en) * | 2003-04-09 | 2008-12-02 | Infineon Technologies Ag | Arithmetic logic unit with merged circuitry for comparison, minimum/maximum selection and saturation for signed and unsigned numbers |
US7395287B2 (en) * | 2003-12-15 | 2008-07-01 | Micrel, Inc. | Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands |
US20060095713A1 (en) * | 2004-11-03 | 2006-05-04 | Stexar Corporation | Clip-and-pack instruction for processor |
US7508329B1 (en) | 2008-01-03 | 2009-03-24 | Micrel, Inc. | Laser controller integrated circuit including variable resolution data processing device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4539549A (en) * | 1982-12-30 | 1985-09-03 | International Business Machines Corporation | Method and apparatus for determining minimum/maximum of multiple data words |
JPS60220402A (ja) * | 1984-04-17 | 1985-11-05 | Mitsubishi Electric Corp | リミツタ装置 |
JPS6211933A (ja) * | 1985-07-09 | 1987-01-20 | Nec Corp | 演算回路 |
JP2600293B2 (ja) * | 1988-06-10 | 1997-04-16 | 日本電気株式会社 | オーバーフロー補正回路 |
US4941119A (en) * | 1988-11-30 | 1990-07-10 | Control Data Corporation | Method and apparatus for predicting an overflow in an integer multiply |
US5164914A (en) * | 1991-01-03 | 1992-11-17 | Hewlett-Packard Company | Fast overflow and underflow limiting circuit for signed adder |
JPH04309123A (ja) * | 1991-04-08 | 1992-10-30 | Nec Corp | 冗長2進演算回路 |
US5422805A (en) * | 1992-10-21 | 1995-06-06 | Motorola, Inc. | Method and apparatus for multiplying two numbers using signed arithmetic |
-
1993
- 1993-12-27 JP JP5346988A patent/JP2591463B2/ja not_active Expired - Lifetime
-
1994
- 1994-12-21 DE DE69427339T patent/DE69427339T2/de not_active Expired - Fee Related
- 1994-12-21 US US08/360,359 patent/US5504697A/en not_active Expired - Fee Related
- 1994-12-21 EP EP94120296A patent/EP0660226B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2591463B2 (ja) | 1997-03-19 |
DE69427339T2 (de) | 2001-09-27 |
EP0660226A3 (de) | 1995-07-19 |
US5504697A (en) | 1996-04-02 |
JPH07191825A (ja) | 1995-07-28 |
EP0660226A2 (de) | 1995-06-28 |
EP0660226B1 (de) | 2001-05-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |