DE69404726D1 - Schnittstellenschaltung - Google Patents

Schnittstellenschaltung

Info

Publication number
DE69404726D1
DE69404726D1 DE69404726T DE69404726T DE69404726D1 DE 69404726 D1 DE69404726 D1 DE 69404726D1 DE 69404726 T DE69404726 T DE 69404726T DE 69404726 T DE69404726 T DE 69404726T DE 69404726 D1 DE69404726 D1 DE 69404726D1
Authority
DE
Germany
Prior art keywords
interface circuit
interface
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69404726T
Other languages
English (en)
Other versions
DE69404726T2 (de
Inventor
Hiroshi Shigehara
Masanori Kinugasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69404726D1 publication Critical patent/DE69404726D1/de
Application granted granted Critical
Publication of DE69404726T2 publication Critical patent/DE69404726T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET
DE69404726T 1993-04-12 1994-04-12 Schnittstellenschaltung Expired - Fee Related DE69404726T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5084507A JP2888722B2 (ja) 1993-04-12 1993-04-12 インターフェース回路

Publications (2)

Publication Number Publication Date
DE69404726D1 true DE69404726D1 (de) 1997-09-11
DE69404726T2 DE69404726T2 (de) 1998-03-19

Family

ID=13832564

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69404726T Expired - Fee Related DE69404726T2 (de) 1993-04-12 1994-04-12 Schnittstellenschaltung

Country Status (5)

Country Link
US (1) US5442307A (de)
EP (1) EP0620650B1 (de)
JP (1) JP2888722B2 (de)
KR (1) KR0136233B1 (de)
DE (1) DE69404726T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3311133B2 (ja) * 1994-02-16 2002-08-05 株式会社東芝 出力回路
US5694075A (en) * 1994-12-30 1997-12-02 Maxim Integrated Products Substrate clamp for non-isolated integrated circuits
US5675809A (en) * 1995-02-10 1997-10-07 Ncr Corporation Voltage control circuit for a dual voltage bus computer system
JP2827963B2 (ja) * 1995-06-02 1998-11-25 日本電気株式会社 半導体集積回路装置
JP3441238B2 (ja) * 1995-06-02 2003-08-25 株式会社東芝 出力回路
US5543733A (en) * 1995-06-26 1996-08-06 Vlsi Technology, Inc. High voltage tolerant CMOS input/output circuit
FR2738424B1 (fr) * 1995-09-05 1997-11-21 Sgs Thomson Microelectronics Interrupteur analogique basse tension
US5808956A (en) * 1995-12-20 1998-09-15 Seiko Epson Corporation Bus-line drive circuit and semiconductor storage device comprising the same
DE69621576T2 (de) * 1995-12-26 2002-12-19 Toshiba Kawasaki Kk Integrierte Halbleiterschaltung
JPH09293789A (ja) * 1996-04-24 1997-11-11 Mitsubishi Electric Corp 半導体集積回路
US5844425A (en) * 1996-07-19 1998-12-01 Quality Semiconductor, Inc. CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations
JP3437719B2 (ja) * 1996-07-24 2003-08-18 株式会社東芝 アナログ・スイッチ回路
US5818099A (en) * 1996-10-03 1998-10-06 International Business Machines Corporation MOS high frequency switch circuit using a variable well bias
TW382670B (en) * 1996-11-21 2000-02-21 Hitachi Ltd Low power processor
JP3746273B2 (ja) * 2003-02-12 2006-02-15 株式会社東芝 信号レベル変換回路
JP3984222B2 (ja) * 2003-12-15 2007-10-03 株式会社東芝 信号レベル変換回路
JP2006071763A (ja) * 2004-08-31 2006-03-16 Fuji Photo Film Co Ltd 科学現象の評価装置、及びその装置を使用した科学現象の評価方法
JP4188933B2 (ja) * 2005-03-29 2008-12-03 富士通マイクロエレクトロニクス株式会社 トレラント入力回路
JP2006301840A (ja) * 2005-04-19 2006-11-02 Toshiba Corp 信号レベル変換バススイッチ
US7567094B2 (en) * 2006-06-14 2009-07-28 Lightwire Inc. Tri-stated driver for bandwidth-limited load
US7826275B2 (en) * 2007-12-10 2010-11-02 Macronix International Co., Ltd. Memory circuit with high reading speed and low switching noise
US10044354B2 (en) * 2016-07-11 2018-08-07 Ricoh Company, Ltd. I/O cell
KR102037903B1 (ko) 2019-08-01 2019-10-29 주식회사 블럭나인 트로이덜 코일 권선장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3720848A (en) * 1971-07-01 1973-03-13 Motorola Inc Solid-state relay
DE3226339C2 (de) * 1981-07-17 1985-12-19 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Analoge Schaltervorrichtung mit MOS-Transistoren
DE3729926A1 (de) * 1987-09-07 1989-03-23 Siemens Ag Cmos-ausgangsstufe
JPH057149A (ja) * 1991-06-27 1993-01-14 Fujitsu Ltd 出力回路
JP3321188B2 (ja) * 1991-07-26 2002-09-03 株式会社東芝 出力回路
US5191244A (en) * 1991-09-16 1993-03-02 Advanced Micro Devices, Inc. N-channel pull-up transistor with reduced body effect

Also Published As

Publication number Publication date
US5442307A (en) 1995-08-15
KR0136233B1 (ko) 1998-05-15
KR940025179A (ko) 1994-11-19
JPH06303126A (ja) 1994-10-28
EP0620650A2 (de) 1994-10-19
DE69404726T2 (de) 1998-03-19
JP2888722B2 (ja) 1999-05-10
EP0620650B1 (de) 1997-08-06
EP0620650A3 (de) 1995-07-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: KRAMER - BARSKE - SCHMIDTCHEN, 81245 MUENCHEN

8339 Ceased/non-payment of the annual fee