KR910016001A - 다이내믹 램(dram)의 비트선 센스 증폭기의 균형 실현 장치 - Google Patents

다이내믹 램(dram)의 비트선 센스 증폭기의 균형 실현 장치 Download PDF

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Publication number
KR910016001A
KR910016001A KR1019900002377A KR900002377A KR910016001A KR 910016001 A KR910016001 A KR 910016001A KR 1019900002377 A KR1019900002377 A KR 1019900002377A KR 900002377 A KR900002377 A KR 900002377A KR 910016001 A KR910016001 A KR 910016001A
Authority
KR
South Korea
Prior art keywords
bit
word line
line sense
balancer
sense amplifiers
Prior art date
Application number
KR1019900002377A
Other languages
English (en)
Other versions
KR930000899B1 (ko
Inventor
오종훈
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019900002377A priority Critical patent/KR930000899B1/ko
Priority to US07/654,245 priority patent/US5255231A/en
Priority to DE4105765A priority patent/DE4105765C2/de
Priority to JP3030192A priority patent/JP2603368B2/ja
Publication of KR910016001A publication Critical patent/KR910016001A/ko
Application granted granted Critical
Publication of KR930000899B1 publication Critical patent/KR930000899B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

내용 없음

Description

다이내믹 램(DRAM)의 비트선 센스 증폭기의 균형 실현 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 워드선 메탈 분사기의 셀 어레이 개략도.

Claims (1)

  1. 폴리실리콘 워드선 상에 병렬로 메탈 워드선을 나열하고 일정수의 행마다 워드선 폴리실리콘과 워드선 메탈을 접속하여 워드선 메탈 분기영역(11)을 형성한 고 집적 반도체 장치에 있어서, 상기 워드선 메탈 분기 영역(11)에 바로 인접한 두 비트선(1,2)을 동일한 행으로 조합하여 하나의 비트선 센스 증폭기(12)에 접속되도록 함을 특징으로 하는 비트선 센스 증폭기의 균형 실현 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900002377A 1990-02-24 1990-02-24 다이나믹 램(dram)의 비트선 센스 증폭기의 균형 실현장치 KR930000899B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019900002377A KR930000899B1 (ko) 1990-02-24 1990-02-24 다이나믹 램(dram)의 비트선 센스 증폭기의 균형 실현장치
US07/654,245 US5255231A (en) 1990-02-24 1991-02-12 Architecture of realizing balance of bit line sense amplifier in DRAM cell array
DE4105765A DE4105765C2 (de) 1990-02-24 1991-02-23 Dynamischer Schreib-/Lesespeicher (DRAM)
JP3030192A JP2603368B2 (ja) 1990-02-24 1991-02-25 ダイナミックラム（ｄｒａｍ）のビット線増幅器の均衡実現構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002377A KR930000899B1 (ko) 1990-02-24 1990-02-24 다이나믹 램(dram)의 비트선 센스 증폭기의 균형 실현장치

Publications (2)

Publication Number Publication Date
KR910016001A true KR910016001A (ko) 1991-09-30
KR930000899B1 KR930000899B1 (ko) 1993-02-11

Family

ID=19296402

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900002377A KR930000899B1 (ko) 1990-02-24 1990-02-24 다이나믹 램(dram)의 비트선 센스 증폭기의 균형 실현장치

Country Status (4)

Country Link
US (1) US5255231A (ko)
JP (1) JP2603368B2 (ko)
KR (1) KR930000899B1 (ko)
DE (1) DE4105765C2 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100273274B1 (ko) * 1998-01-21 2001-01-15 김영환 오버 드라이빙 제어회로
US5909388A (en) * 1998-03-31 1999-06-01 Siemens Aktiengesellschaft Dynamic random access memory circuit and methods therefor
US6084816A (en) 1998-04-16 2000-07-04 Kabushiki Kaisha Toshiba Semiconductor memory device
JPH11330414A (ja) * 1998-05-14 1999-11-30 Oki Electric Ind Co Ltd 半導体メモリ装置
KR100402245B1 (ko) 2001-09-18 2003-10-17 주식회사 하이닉스반도체 메모리 장치
US7606097B2 (en) * 2006-12-27 2009-10-20 Micron Technology, Inc. Array sense amplifiers, memory devices and systems including same, and methods of operation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3942164A (en) * 1975-01-30 1976-03-02 Semi, Inc. Sense line coupling reduction system
US4460981A (en) * 1981-12-24 1984-07-17 Intel Corporation Virtual ground memory
JPS6282597A (ja) * 1985-10-08 1987-04-16 Fujitsu Ltd 半導体記憶装置
JPS63153792A (ja) * 1986-12-17 1988-06-27 Sharp Corp 半導体メモリ装置
JP2751298B2 (ja) * 1989-01-26 1998-05-18 日本電気株式会社 半導体記憶装置
JP2743459B2 (ja) * 1989-04-27 1998-04-22 日本電気株式会社 半導体記憶装置
JPH06188261A (ja) * 1992-12-18 1994-07-08 Ricoh Co Ltd Ｌｄｄ構造の半導体装置とその製造方法

Also Published As

Publication number Publication date
JPH04215472A (ja) 1992-08-06
US5255231A (en) 1993-10-19
DE4105765C2 (de) 2000-01-20
JP2603368B2 (ja) 1997-04-23
DE4105765A1 (de) 1991-08-29
KR930000899B1 (ko) 1993-02-11

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