KR890012320A - 반도체기억장치 - Google Patents

반도체기억장치 Download PDF

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Publication number
KR890012320A
KR890012320A KR1019890000528A KR890000528A KR890012320A KR 890012320 A KR890012320 A KR 890012320A KR 1019890000528 A KR1019890000528 A KR 1019890000528A KR 890000528 A KR890000528 A KR 890000528A KR 890012320 A KR890012320 A KR 890012320A
Authority
KR
South Korea
Prior art keywords
data line
line pairs
main data
memory device
semiconductor memory
Prior art date
Application number
KR1019890000528A
Other languages
English (en)
Inventor
마사루 고야나기
Original Assignee
야오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 야오이 죠이치, 가부시키가이샤 도시바 filed Critical 야오이 죠이치
Publication of KR890012320A publication Critical patent/KR890012320A/ko

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4097Bit-line organisation, e.g. bit-line layout, folded bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

내용 없음.

Description

반도체기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 제 1 실시예를 관한 반도체기억장치를 도시해 놓은 구성도,
제 2 도 내지 제 5 도는 본 발명의 제 2 실시예 내지 제 5 실시예에 관한 반도체기억장치를 도시해 놓은 구성도.

Claims (5)

  1. 행 및 열의 매트릭스형상에 복수의 메모리셀이 배치된 메모리셀어레이를 갖는 반도체기억장치에 있어서, 열방향으로 복수로 분할되어 그 각각에 복수의 메모리셀이 접속되는 복수의 분할데이터선쌍(BS31,BS32…)과, 이들 복수의 분할데이터쌍(BS31,BS32…)에 실질적으로 평행되게 배치되어 데이터입출력선에 결합되는 주데이터선쌍(B31,B32…), 상기 각 분할데이터선쌍(BS31,BS32…)과 상기 주데이터선쌍(B31,B32…)의 주데이터선 사이에 각각 삽입되어 그들 사이의 결합을 제어해주는 제 1 스위치수단(S31,S32…) 및, 상기 복수의 분할데이터선쌍(BS31,BS32…)중 열방향에 인접하는 2개의 분할데이터선쌍(BS31)(BS32)사이에 설치되는 감지증폭기(SA31…)를 구비한 것을 특징으로 하는 반도체기억장치.
  2. 제 1 항에 있어서, 상기 감지증폭기가 상기 복수의 분할데이터선쌍마다 각각 독립되게 설치되면서 상기 분할데이터선쌍에 직접 접속된 것을 특징으로 하는 반도체기억장치.
  3. 제 2 항에 있어서, 상기 주데이터선쌍의 한쪽 주데이터선이, 그에 인접하는 열의 한쪽 주데이터선으로 공통되게 사용되도록 된 것을 특징으로 하는 반도체기억장치.
  4. 제 2 항에 있어서, 상기 주데이터선쌍이, 그에 인접하는 열의 주데이터선쌍으로서 공통으로 사용되도록 된 것을 특징으로 하는 반도체기억장치.
  5. 제 1 항에 있어서, 상기 감지증폭기(SA31…)와 이를 끼우는 상기 2개의 분할데이터선쌍(BS31,BS32)사이에 각각 그들 사이의 결합을 제어해 주는 제 2 스위치수단(SS31,SS32…)이 삽입되어진 것을 특징으로 하는 반도체기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890000528A 1988-01-19 1989-01-19 반도체기억장치 KR890012320A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63008912A JPH01184787A (ja) 1988-01-19 1988-01-19 半導体メモリ
JP63-8912 1988-01-19

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR2019930001774U Division KR930008700Y1 (ko) 1988-01-19 1993-02-11 반도체 기억장치

Publications (1)

Publication Number Publication Date
KR890012320A true KR890012320A (ko) 1989-08-25

Family

ID=11705873

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1019890000528A KR890012320A (ko) 1988-01-19 1989-01-19 반도체기억장치
KR2019930001774U KR930008700Y1 (ko) 1988-01-19 1993-02-11 반도체 기억장치

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR2019930001774U KR930008700Y1 (ko) 1988-01-19 1993-02-11 반도체 기억장치

Country Status (3)

Country Link
US (1) US4970685A (ko)
JP (1) JPH01184787A (ko)
KR (2) KR890012320A (ko)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101554B2 (ja) * 1988-11-29 1995-11-01 三菱電機株式会社 半導体記憶装置およびそのデータ転送方法
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
JP2624569B2 (ja) * 1990-10-22 1997-06-25 シャープ株式会社 読出し専用メモリ
US5457647A (en) * 1993-03-31 1995-10-10 Sgs-Thomson Microelectronics, Inc. Passive hierarchical bitline memory architecture which resides in metal layers of a SRAM array
US5715189A (en) * 1993-04-13 1998-02-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having hierarchical bit line arrangement
US5734620A (en) * 1995-04-05 1998-03-31 Micron Technology, Inc. Hierarchical memory array structure with redundant components having electrically isolated bit lines
US5600602A (en) * 1995-04-05 1997-02-04 Micron Technology, Inc. Hierarchical memory array structure having electrically isolated bit lines for temporary data storage
DE69700241T2 (de) * 1996-03-01 1999-11-04 Mitsubishi Denki K.K., Tokio/Tokyo Halbleiterspeichergerät, um Fehlfunktion durch Zeilenauswahlleitungsunterbrechung zu vermeiden
US5894437A (en) * 1998-01-23 1999-04-13 Hyundai Elecronics America, Inc. Concurrent read/write architecture for a flash memory
US6479851B1 (en) * 2000-05-16 2002-11-12 Hynix Semiconductor, Inc. Memory device with divided bit-line architecture
JP2003257180A (ja) * 2002-03-04 2003-09-12 Nec Electronics Corp DRAM(DynamicRandomAccessMemory)及びその動作方法
JP5063912B2 (ja) * 2006-03-31 2012-10-31 パナソニック株式会社 半導体記憶装置
WO2014080756A1 (ja) * 2012-11-22 2014-05-30 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
CA3221253A1 (en) 2015-11-12 2017-05-12 Whitewater West Industries Ltd. Method and apparatus for fastening of inflatable ride surfaces

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942399B2 (ja) * 1979-12-21 1984-10-15 株式会社日立製作所 メモリ装置
US4351034A (en) * 1980-10-10 1982-09-21 Inmos Corporation Folded bit line-shared sense amplifiers
JPS57198592A (en) * 1981-05-29 1982-12-06 Hitachi Ltd Semiconductor memory device
JPS5880189A (ja) * 1981-11-05 1983-05-14 Fujitsu Ltd 半導体記憶装置
EP0101884A3 (en) * 1982-07-21 1987-09-02 Hitachi, Ltd. Monolithic semiconductor memory
JPS6148194A (ja) * 1984-08-15 1986-03-08 Fujitsu Ltd 半導体記憶装置
JPH07109708B2 (ja) * 1985-04-19 1995-11-22 日立超エル・エス・アイ・エンジニアリング株式会社 ダイナミツク型ram
JPS62120697A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd 半導体記憶装置
JPS6363197A (ja) * 1986-09-03 1988-03-19 Toshiba Corp 半導体記憶装置
US4819207A (en) * 1986-09-30 1989-04-04 Kabushiki Kaisha Toshiba High-speed refreshing rechnique for highly-integrated random-access memory

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Publication number Publication date
KR930008700Y1 (ko) 1993-12-28
US4970685A (en) 1990-11-13
JPH01184787A (ja) 1989-07-24

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