KR910015060A - 자기 정열을 이용한 ccd 채널의 제조방법 - Google Patents

자기 정열을 이용한 ccd 채널의 제조방법 Download PDF

Info

Publication number
KR910015060A
KR910015060A KR1019900000948A KR900000948A KR910015060A KR 910015060 A KR910015060 A KR 910015060A KR 1019900000948 A KR1019900000948 A KR 1019900000948A KR 900000948 A KR900000948 A KR 900000948A KR 910015060 A KR910015060 A KR 910015060A
Authority
KR
South Korea
Prior art keywords
polysilicon
alignment
ccd channel
magnetic alignment
ion implantation
Prior art date
Application number
KR1019900000948A
Other languages
English (en)
Other versions
KR930000720B1 (ko
Inventor
박용
이서규
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900000948A priority Critical patent/KR930000720B1/ko
Priority to US07/553,170 priority patent/US5024963A/en
Priority to DE4041014A priority patent/DE4041014C2/de
Priority to GB9101809A priority patent/GB2240430B/en
Priority to FR9100917A priority patent/FR2657727B1/fr
Priority to JP3026787A priority patent/JPH0785505B2/ja
Publication of KR910015060A publication Critical patent/KR910015060A/ko
Application granted granted Critical
Publication of KR930000720B1 publication Critical patent/KR930000720B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946—Charge transfer devices
    • H01L29/66954—Charge transfer devices with an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1062—Channel region of field-effect devices of charge coupled devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76833—Buried channel CCD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76833—Buried channel CCD
    • H01L29/76841—Two-Phase CCD

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

내용 없음

Description

자기 정열을 이용한 CCD채널의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명 CCD채널을 나타낸 것으로 (가)는 제1도의 (가)의 A-A단면도 및 포텐셜 설명도, (나)는 제1도 (가)는 B-B단면도 및 포텐셜 설명도, 제3도는 본 발명의 CCD채널 제조공정 순서도.

Claims (1)

  1. 액티브 영역(1)에 이온주입으로 첫번째 폴리실리콘(2)을 디포지션 하고 포토공정 실시후 상기 폴리실리콘(2)을 에칭하며 두번째 이온주입을 위한 포토공정 실시후 상기 폴리실리콘(2)에 자기정열을 실시하고 세번째 이온주입을 위한 포토공정 실시후 상기 첫번째 폴리실리콘(2)에 자기정열을 실시하며 다시 상기의 두번째 이온주입을 위한 포토공정으로부터 첫번째 폴리실리콘(2)에 자기정열 반복실시후 두번째 폴리실리콘(5)을 디포지션하여 이 두번째 폴리실리콘(5) 아래에 멀티 포텐셜을 갖게함을 특징으로 하는 자기 정열을 이용한 CCD채널의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900000948A 1990-01-29 1990-01-29 자기정열을 이용한 ccd 채널의 제조방법 KR930000720B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019900000948A KR930000720B1 (ko) 1990-01-29 1990-01-29 자기정열을 이용한 ccd 채널의 제조방법
US07/553,170 US5024963A (en) 1990-01-29 1990-07-16 Method of fabricating a BCCD channel with stair-case doping by self-alignment
DE4041014A DE4041014C2 (de) 1990-01-29 1990-12-20 Verfahren zur Herstellung eines ladungsgekoppelten Halbleiterbauelements mit vergrabenem Kanal (BCCD)
GB9101809A GB2240430B (en) 1990-01-29 1991-01-28 Method for fabricating a CCD channel by self-alignment
FR9100917A FR2657727B1 (fr) 1990-01-29 1991-01-28 Procede pour realiser un canal de dispositif a transfert de charges.
JP3026787A JPH0785505B2 (ja) 1990-01-29 1991-01-29 自己整合によりｃｃｄチャンネルを作製する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900000948A KR930000720B1 (ko) 1990-01-29 1990-01-29 자기정열을 이용한 ccd 채널의 제조방법

Publications (2)

Publication Number Publication Date
KR910015060A true KR910015060A (ko) 1991-08-31
KR930000720B1 KR930000720B1 (ko) 1993-01-30

Family

ID=19295570

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900000948A KR930000720B1 (ko) 1990-01-29 1990-01-29 자기정열을 이용한 ccd 채널의 제조방법

Country Status (6)

Country Link
US (1) US5024963A (ko)
JP (1) JPH0785505B2 (ko)
KR (1) KR930000720B1 (ko)
DE (1) DE4041014C2 (ko)
FR (1) FR2657727B1 (ko)
GB (1) GB2240430B (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359767B1 (ko) 1998-07-11 2002-11-07 주식회사 하이닉스반도체 고체촬상소자의 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577964A (en) * 1980-06-17 1982-01-16 Matsushita Electric Ind Co Ltd Charge transfer element
US4362575A (en) * 1981-08-27 1982-12-07 Rca Corporation Method of making buried channel charge coupled device with means for controlling excess charge
US4396438A (en) * 1981-08-31 1983-08-02 Rca Corporation Method of making CCD imagers
JPH0618263B2 (ja) * 1984-02-23 1994-03-09 日本電気株式会社 電荷転送素子
US4667213A (en) * 1984-09-24 1987-05-19 Rca Corporation Charge-coupled device channel structure
DE3581793D1 (de) * 1984-12-06 1991-03-28 Toshiba Kawasaki Kk Ladungsverschiebeanordnung.
US4642877A (en) * 1985-07-01 1987-02-17 Texas Instruments Incorporated Method for making charge coupled device (CCD)-complementary metal oxide semiconductor (CMOS) devices
JP2565257B2 (ja) * 1987-06-16 1996-12-18 ソニー株式会社 電荷転送装置
US4992842A (en) * 1988-07-07 1991-02-12 Tektronix, Inc. Charge-coupled device channel with countinously graded built-in potential

Also Published As

Publication number Publication date
GB2240430A (en) 1991-07-31
FR2657727A1 (fr) 1991-08-02
DE4041014A1 (de) 1991-08-01
GB2240430B (en) 1993-11-17
JPH04212429A (ja) 1992-08-04
US5024963A (en) 1991-06-18
JPH0785505B2 (ja) 1995-09-13
FR2657727B1 (fr) 1995-11-17
GB9101809D0 (en) 1991-03-13
KR930000720B1 (ko) 1993-01-30
DE4041014C2 (de) 2001-05-10

Similar Documents

Publication Publication Date Title
KR910015060A (ko) 자기 정열을 이용한 ccd 채널의 제조방법
KR920005296A (ko) 반도체 소자분리 제조방법
KR910001943A (ko) 바이포울러 씨모스의 제조방법
KR920001743A (ko) Ldd구조 및 제조방법
KR920007071A (ko) 매몰산화를 이용한 트렌치 격리영역 형성방법
KR910013550A (ko) 고용량 스택 셀 제조방법
KR910001930A (ko) 자기정렬된 저도핑된 접합형성방법
KR910005385A (ko) 대칭적 포물선 정션 형성 방법
KR930003351A (ko) 씨모스 인버터 구조 및 그 제조방법
KR970052987A (ko) 반도체장치의 웰(well) 형성방법
KR910019204A (ko) 슬롭형 게이트를 이용한 ldd제조방법
KR910017635A (ko) 메모리 셀 커패시터 제조방법
KR910005441A (ko) 실리사이드를 사용한 매설 접촉 형성방법
KR910005483A (ko) 캐패시터 제조 방법
KR920003467A (ko) 필드산화막 형성방법
KR920005295A (ko) Locos 격리 방법
KR910013426A (ko) 디램의 트랜지스터 제조방법
KR920003560A (ko) 모스트랜지스터의 오토도핑에 의한 n+s/d 형성방법
KR920003468A (ko) 2층의 다결정 실리콘막을 이용한 모스 제조방법
KR930015081A (ko) 얕은 접합 모스패트 제조방법
KR920013749A (ko) 수직형 시모스 제조방법
KR910013510A (ko) 이중 트랜치 공정에 의한 기억소자의 제조방법
KR970053440A (ko) 반도체의 소자격리방법
KR910017684A (ko) 메모리 셀 커패시터 제조방법
KR970052145A (ko) 반도체 장치의 이중 웰(twin well) 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090102

Year of fee payment: 17

EXPY Expiration of term