KR910007099B1 - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR910007099B1
KR910007099B1 KR1019880006507A KR880006507A KR910007099B1 KR 910007099 B1 KR910007099 B1 KR 910007099B1 KR 1019880006507 A KR1019880006507 A KR 1019880006507A KR 880006507 A KR880006507 A KR 880006507A KR 910007099 B1 KR910007099 B1 KR 910007099B1
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KR
South Korea
Prior art keywords
layer
forming
semiconductor
manufacturing
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019880006507A
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English (en)
Korean (ko)
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KR880014657A (ko
Inventor
마사가즈 가쿠마
테츠야 아사미
Original Assignee
가부시키가이샤 도시바
아오이 죠이치
도시바 마이콤엔지니어링 가부시키가이샤
다케다이 마사다카
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 도시바, 아오이 죠이치, 도시바 마이콤엔지니어링 가부시키가이샤, 다케다이 마사다카 filed Critical 가부시키가이샤 도시바
Publication of KR880014657A publication Critical patent/KR880014657A/ko
Application granted granted Critical
Publication of KR910007099B1 publication Critical patent/KR910007099B1/ko
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019880006507A 1987-05-29 1988-05-28 반도체장치의 제조방법 Expired KR910007099B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62133797A JPS63299251A (ja) 1987-05-29 1987-05-29 半導体装置の製造方法
JP62-133797 1987-05-29
JP?62-133797 1987-05-29

Publications (2)

Publication Number Publication Date
KR880014657A KR880014657A (ko) 1988-12-24
KR910007099B1 true KR910007099B1 (ko) 1991-09-18

Family

ID=15113248

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880006507A Expired KR910007099B1 (ko) 1987-05-29 1988-05-28 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US4800176A (enExample)
JP (1) JPS63299251A (enExample)
KR (1) KR910007099B1 (enExample)

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63268258A (ja) * 1987-04-24 1988-11-04 Nec Corp 半導体装置
US5594280A (en) * 1987-10-08 1997-01-14 Anelva Corporation Method of forming a thin film and apparatus of forming a metal thin film utilizing temperature controlling means
US5185283A (en) * 1987-10-22 1993-02-09 Matsushita Electronics Corporation Method of making master slice type integrated circuit device
JPH077783B2 (ja) * 1988-03-18 1995-01-30 株式会社東芝 電気的接続部に銅もしくは銅合金製金属細線を配置する半導体装置
US5008730A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Contact stud structure for semiconductor devices
US5008216A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Process for improved contact stud structure for semiconductor devices
US5204276A (en) * 1988-12-06 1993-04-20 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US4888087A (en) * 1988-12-13 1989-12-19 The Board Of Trustees Of The Leland Stanford Junior University Planarized multilevel interconnection for integrated circuits
DE3915337A1 (de) * 1989-05-10 1990-11-15 Siemens Ag Verfahren zum herstellen einer niederohmigen planen kontaktmetallisierung fuer hochintegrierte halbleiterschaltungen
US5552627A (en) * 1990-04-12 1996-09-03 Actel Corporation Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers
US5614756A (en) * 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5780323A (en) * 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JPH0680638B2 (ja) * 1990-07-05 1994-10-12 株式会社東芝 半導体装置の製造方法
EP0469214A1 (en) * 1990-07-31 1992-02-05 International Business Machines Corporation Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom
DE69023765T2 (de) * 1990-07-31 1996-06-20 Ibm Verfahren zur Herstellung von Bauelementen mit übereinander angeordneten Feldeffekttransistoren mit Wolfram-Gitter und sich daraus ergebende Struktur.
DE69026503T2 (de) * 1990-07-31 1996-11-14 Ibm Verfahren zur Herstellung von Bauelementen mit übereinander angeordneten selbstjustierten Feldeffekttransistoren aus Polisilizium und sich daraus ergebende Struktur
US5059555A (en) * 1990-08-20 1991-10-22 National Semiconductor Corporation Method to fabricate vertical fuse devices and Schottky diodes using thin sacrificial layer
KR100228259B1 (ko) * 1990-10-24 1999-11-01 고지마 마따오 박막의 형성방법 및 반도체장치
US5244538A (en) * 1991-07-26 1993-09-14 Microelectronics And Computer Technology Corporation Method of patterning metal on a substrate using direct-write deposition of a mask
US5382315A (en) * 1991-02-11 1995-01-17 Microelectronics And Computer Technology Corporation Method of forming etch mask using particle beam deposition
EP0509631A1 (en) * 1991-04-18 1992-10-21 Actel Corporation Antifuses having minimum areas
US5290734A (en) * 1991-06-04 1994-03-01 Vlsi Technology, Inc. Method for making anti-fuse structures
JP3166221B2 (ja) * 1991-07-23 2001-05-14 日本電気株式会社 半導体装置及びその製造方法
JP2887985B2 (ja) * 1991-10-18 1999-05-10 日本電気株式会社 半導体装置及びその製造方法
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
EP0558304B1 (en) * 1992-02-28 2000-01-19 STMicroelectronics, Inc. Method of forming submicron contacts
JP3413876B2 (ja) * 1992-07-08 2003-06-09 セイコーエプソン株式会社 半導体装置
US5480815A (en) * 1992-08-19 1996-01-02 Nec Corporation Method of manufacturing a biopolar transistor in which an emitter region is formed by impurities supplied from double layered polysilicon
KR940010197A (ko) * 1992-10-13 1994-05-24 김광호 반도체 장치의 제조방법
US5308795A (en) * 1992-11-04 1994-05-03 Actel Corporation Above via metal-to-metal antifuse
DE4240962C1 (de) * 1992-12-05 1994-04-07 Erno Raumfahrttechnik Gmbh Triebwerk
US5550404A (en) * 1993-05-20 1996-08-27 Actel Corporation Electrically programmable antifuse having stair aperture
US5414364A (en) * 1993-09-08 1995-05-09 Actel Corporation Apparatus and method for measuring programmed antifuse resistance
JP2684978B2 (ja) * 1993-11-25 1997-12-03 日本電気株式会社 半導体装置
JP2555964B2 (ja) * 1993-12-10 1996-11-20 日本電気株式会社 アライメント精度調査パターン
US5541137A (en) * 1994-03-24 1996-07-30 Micron Semiconductor Inc. Method of forming improved contacts from polysilicon to silicon or other polysilicon layers
US5469396A (en) * 1994-06-07 1995-11-21 Actel Corporation Apparatus and method determining the resistance of antifuses in an array
US5624870A (en) * 1995-03-16 1997-04-29 United Microelectronics Corporation Method of contact planarization
US5510296A (en) * 1995-04-27 1996-04-23 Vanguard International Semiconductor Corporation Manufacturable process for tungsten polycide contacts using amorphous silicon
EP0774164A1 (en) * 1995-06-02 1997-05-21 Actel Corporation Raised tungsten plug antifuse and fabrication process
US5858873A (en) * 1997-03-12 1999-01-12 Lucent Technologies Inc. Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof
US6312997B1 (en) * 1998-08-12 2001-11-06 Micron Technology, Inc. Low voltage high performance semiconductor devices and methods
US6774667B1 (en) 2002-05-09 2004-08-10 Actel Corporation Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays
US7378867B1 (en) 2002-06-04 2008-05-27 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US6891394B1 (en) * 2002-06-04 2005-05-10 Actel Corporation Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US6759731B2 (en) * 2002-06-05 2004-07-06 United Microelectronics Corp. Bipolar junction transistor and fabricating method
US6765427B1 (en) 2002-08-08 2004-07-20 Actel Corporation Method and apparatus for bootstrapping a programmable antifuse circuit
US7434080B1 (en) * 2002-09-03 2008-10-07 Actel Corporation Apparatus for interfacing and testing a phase locked loop in a field programmable gate array
US6750674B1 (en) 2002-10-02 2004-06-15 Actel Corporation Carry chain for use between logic modules in a field programmable gate array
US7269814B1 (en) 2002-10-08 2007-09-11 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US6885218B1 (en) 2002-10-08 2005-04-26 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US6727726B1 (en) 2002-11-12 2004-04-27 Actel Corporation Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array
US6946871B1 (en) 2002-12-18 2005-09-20 Actel Corporation Multi-level routing architecture in a field programmable gate array having transmitters and receivers
US6891396B1 (en) 2002-12-27 2005-05-10 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
US7385420B1 (en) 2002-12-27 2008-06-10 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
US6825690B1 (en) 2003-05-28 2004-11-30 Actel Corporation Clock tree network in a field programmable gate array
US7375553B1 (en) 2003-05-28 2008-05-20 Actel Corporation Clock tree network in a field programmable gate array
US6838902B1 (en) 2003-05-28 2005-01-04 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US7385419B1 (en) * 2003-05-30 2008-06-10 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US6867615B1 (en) 2003-05-30 2005-03-15 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2537779B1 (fr) * 1982-12-10 1986-03-14 Commissariat Energie Atomique Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre
EP0139549B1 (fr) * 1983-08-12 1988-12-28 Commissariat A L'energie Atomique Procédé de positionnement d'une ligne d'interconnexion sur un trou de contact électrique d'un circuit intégré
FR2566181B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
JPS6142714A (ja) * 1984-08-02 1986-03-01 Fuji Photo Film Co Ltd 多層導体膜構造体の製造方法

Also Published As

Publication number Publication date
JPS63299251A (ja) 1988-12-06
US4800176A (en) 1989-01-24
JPH0424861B2 (enExample) 1992-04-28
KR880014657A (ko) 1988-12-24

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