KR900019220A - 반도체장치 - Google Patents
반도체장치 Download PDFInfo
- Publication number
- KR900019220A KR900019220A KR1019890007065A KR890007065A KR900019220A KR 900019220 A KR900019220 A KR 900019220A KR 1019890007065 A KR1019890007065 A KR 1019890007065A KR 890007065 A KR890007065 A KR 890007065A KR 900019220 A KR900019220 A KR 900019220A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive layers
- semiconductor device
- insulating film
- conductive
- propagate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 반도체장치의 단면도, 제2도는 제1도에 도시된 반도체장치의 등가회로도, 제3도는 본 발명의 단른 실시예에 따른 반도체장치의 단면도.
Claims (1)
- 반도체기판(1, 11)상에 형성되어 아나로그신호 또는 디지털신호를 전파시키는 제1전도층(2, 12)과, 이 제1도전층(2, 12)의 윗쪽 또는 아랫쪽에 절연막(4, 14)을 매개로 서로 포개지게끔 형성되어 아나로그신호 전파시키는 제2도전층(3, 13), 상기 제1도전층(2, 12)과 상기 제2도전층(3, 13)간에 상기 절연막(4, 14)을 매개로 형성되어 전위를 고정시키는 제3도전층(5, 15)을 구비하여 구성된 것을 특징으로 하는 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63-128780 | 1988-05-26 | ||
JP63128780A JPH01297839A (ja) | 1988-05-26 | 1988-05-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900019220A true KR900019220A (ko) | 1990-12-24 |
KR920008420B1 KR920008420B1 (ko) | 1992-09-28 |
Family
ID=14993278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890007065A KR920008420B1 (ko) | 1988-05-26 | 1989-05-26 | 반도체장치 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0353414A3 (ko) |
JP (1) | JPH01297839A (ko) |
KR (1) | KR920008420B1 (ko) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0473144A3 (en) * | 1990-08-28 | 1992-04-15 | Nec Corporation | Semiconductor integrated circuit comprising interconnections |
US5196920A (en) * | 1992-04-21 | 1993-03-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks |
US5663677A (en) * | 1995-03-30 | 1997-09-02 | Lucent Technologies Inc. | Integrated circuit multi-level interconnection technique |
EP0837503A3 (en) * | 1996-10-16 | 1998-07-15 | Digital Equipment Corporation | Reference plane metallization on an integrated circuit |
FR2768852B1 (fr) * | 1997-09-22 | 1999-11-26 | Sgs Thomson Microelectronics | Realisation d'un condensateur intermetallique |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5339084A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Silicon gate mis semiconductor device |
JPS584820B2 (ja) * | 1977-04-20 | 1983-01-27 | 松下電器産業株式会社 | 半導体装置 |
EP0033130B1 (en) * | 1980-01-25 | 1986-01-08 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JPS5780828A (en) * | 1980-11-07 | 1982-05-20 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS5994849A (ja) * | 1982-11-24 | 1984-05-31 | Nec Corp | 半導体集積回路装置 |
JPS60192359A (ja) * | 1984-03-14 | 1985-09-30 | Nec Corp | 半導体メモリ装置 |
JPS60206161A (ja) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | 半導体集積回路 |
-
1988
- 1988-05-26 JP JP63128780A patent/JPH01297839A/ja active Pending
-
1989
- 1989-05-26 KR KR1019890007065A patent/KR920008420B1/ko not_active IP Right Cessation
- 1989-05-26 EP EP19890109477 patent/EP0353414A3/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JPH01297839A (ja) | 1989-11-30 |
EP0353414A2 (en) | 1990-02-07 |
EP0353414A3 (en) | 1990-10-31 |
KR920008420B1 (ko) | 1992-09-28 |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030901 Year of fee payment: 12 |
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LAPS | Lapse due to unpaid annual fee |