KR900015302A - 평탄화 표면을 가지는 반도체장치의 제조방법 - Google Patents

평탄화 표면을 가지는 반도체장치의 제조방법

Info

Publication number
KR900015302A
KR900015302A KR1019900003740A KR900003740A KR900015302A KR 900015302 A KR900015302 A KR 900015302A KR 1019900003740 A KR1019900003740 A KR 1019900003740A KR 900003740 A KR900003740 A KR 900003740A KR 900015302 A KR900015302 A KR 900015302A
Authority
KR
South Korea
Prior art keywords
manufacturing
semiconductor device
flattening surface
flattening
semiconductor
Prior art date
Application number
KR1019900003740A
Other languages
English (en)
Other versions
KR940001889B1 (ko
Inventor
다쓰야 미세
Original Assignee
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤 filed Critical 후지쓰 가부시끼가이샤
Publication of KR900015302A publication Critical patent/KR900015302A/ko
Application granted granted Critical
Publication of KR940001889B1 publication Critical patent/KR940001889B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019900003740A 1989-03-20 1990-03-20 평탄화(平坦化) 표면을 가지는 반도체장치의 제조방법 KR940001889B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6865689 1989-03-20
JP1-68656 1989-03-20

Publications (2)

Publication Number Publication Date
KR900015302A true KR900015302A (ko) 1990-10-26
KR940001889B1 KR940001889B1 (ko) 1994-03-10

Family

ID=13379964

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900003740A KR940001889B1 (ko) 1989-03-20 1990-03-20 평탄화(平坦化) 표면을 가지는 반도체장치의 제조방법

Country Status (3)

Country Link
US (2) US5068711A (ko)
EP (1) EP0388862B1 (ko)
KR (1) KR940001889B1 (ko)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2518435B2 (ja) * 1990-01-29 1996-07-24 ヤマハ株式会社 多層配線形成法
JPH073835B2 (ja) * 1990-03-19 1995-01-18 日本プレシジョン・サーキッツ株式会社 半導体装置
JPH0834304B2 (ja) * 1990-09-20 1996-03-29 富士通株式会社 半導体装置およびその製造方法
KR920015542A (ko) * 1991-01-14 1992-08-27 김광호 반도체장치의 다층배선형성법
US5285102A (en) * 1991-07-25 1994-02-08 Texas Instruments Incorporated Method of forming a planarized insulation layer
DE69228099T2 (de) * 1991-09-23 1999-05-20 Sgs Thomson Microelectronics Verfahren zur Herstellung von Sacklöchern und hergestellte Struktur
US5246883A (en) * 1992-02-06 1993-09-21 Sgs-Thomson Microelectronics, Inc. Semiconductor contact via structure and method
JPH05235184A (ja) * 1992-02-26 1993-09-10 Nec Corp 半導体装置の多層配線構造体の製造方法
US5384483A (en) * 1992-02-28 1995-01-24 Sgs-Thomson Microelectronics, Inc. Planarizing glass layer spaced from via holes
US5317192A (en) * 1992-05-06 1994-05-31 Sgs-Thomson Microelectronics, Inc. Semiconductor contact via structure having amorphous silicon side walls
US5344797A (en) * 1992-10-30 1994-09-06 At&T Bell Laboratories Method of forming interlevel dielectric for integrated circuits
US6570221B1 (en) * 1993-07-27 2003-05-27 Hyundai Electronics America Bonding of silicon wafers
US5847457A (en) * 1993-11-12 1998-12-08 Stmicroelectronics, Inc. Structure and method of forming vias
US5399533A (en) * 1993-12-01 1995-03-21 Vlsi Technology, Inc. Method improving integrated circuit planarization during etchback
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5453403A (en) * 1994-10-24 1995-09-26 Chartered Semiconductor Manufacturing Pte, Ltd. Method of beveled contact opening formation
KR0161731B1 (ko) * 1994-10-28 1999-02-01 김주용 반도체소자의 미세콘택 형성방법
US6083831A (en) 1996-03-26 2000-07-04 Micron Technology, Inc. Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor
JP3961044B2 (ja) * 1996-05-14 2007-08-15 シャープ株式会社 電子回路装置
KR100230405B1 (ko) 1997-01-30 1999-11-15 윤종용 반도체장치의 다층 배선 형성방법
US6294456B1 (en) * 1998-11-27 2001-09-25 Taiwan Semiconductor Manufacturing Company Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule
US6835645B2 (en) * 2000-11-29 2004-12-28 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US7455955B2 (en) * 2002-02-27 2008-11-25 Brewer Science Inc. Planarization method for multi-layer lithography processing

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54149469A (en) * 1978-05-16 1979-11-22 Toshiba Corp Semiconductor device
DE2967538D1 (en) * 1978-06-14 1985-12-05 Fujitsu Ltd Process for producing a semiconductor device having an insulating layer of silicon dioxide covered by a film of silicon oxynitride
JPS5636143A (en) * 1979-08-31 1981-04-09 Hitachi Ltd Manufacture of semiconductor device
US4470062A (en) * 1979-08-31 1984-09-04 Hitachi, Ltd. Semiconductor device having isolation regions
JPS56150830A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device
JPS5943545A (ja) * 1982-09-06 1984-03-10 Hitachi Ltd 半導体集積回路装置
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
US4708770A (en) * 1986-06-19 1987-11-24 Lsi Logic Corporation Planarized process for forming vias in silicon wafers
US4920070A (en) * 1987-02-19 1990-04-24 Fujitsu Limited Method for forming wirings for a semiconductor device by filling very narrow via holes
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
US4920072A (en) * 1988-10-31 1990-04-24 Texas Instruments Incorporated Method of forming metal interconnects

Also Published As

Publication number Publication date
US5068711A (en) 1991-11-26
US5155064A (en) 1992-10-13
KR940001889B1 (ko) 1994-03-10
EP0388862B1 (en) 1995-07-12
EP0388862A3 (en) 1991-01-02
EP0388862A2 (en) 1990-09-26

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