KR900005564A - 반도체장치 및 제조방법 - Google Patents

반도체장치 및 제조방법 Download PDF

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KR900005564A
KR900005564A KR1019880012889A KR880012889A KR900005564A KR 900005564 A KR900005564 A KR 900005564A KR 1019880012889 A KR1019880012889 A KR 1019880012889A KR 880012889 A KR880012889 A KR 880012889A KR 900005564 A KR900005564 A KR 900005564A
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film
bit line
glass
doped
semiconductor device
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KR1019880012889A
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KR910008835B1 (ko
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김의송
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강진구
삼성반도체통신 주식회사
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Priority to KR1019880012889A priority Critical patent/KR910008835B1/ko
Priority to US07/411,705 priority patent/US5071790A/en
Priority to JP1252520A priority patent/JP2918167B2/ja
Publication of KR900005564A publication Critical patent/KR900005564A/ko
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Publication of KR910008835B1 publication Critical patent/KR910008835B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음.

Description

반도체장치 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의해 개량된 반도체장치의 컨택부위의 도식적인 부분 단면도.
제4도는 본 발명에 의해 개량된 반도체장치의 부분 단면도로써, a부터 d까지의 순서로 제조공정의 순서를 도식적으로 나타낸 제조공정흐름도.

Claims (5)

  1. 비트라인과 메탈전극사이에 층간절연막을 사용하는 반도체장치에 있어서, 비트라인(6)과 메탈전극(9) 사이의 절연성을 보강하기 위하여, 상기 비트라인(6)과 층간 절연막(8) 사이에 상기 층간절연막(8)과 식각비율이 동일한 플라즈마 옥시 나이트라이드막(7)을 형성시킨 것을 특징으로 하는 반도체장치.
  2. 청구범위 제1항에 있어서, 층간절연막이 붕소 실리게이트 글래스(BSG), 비소 실리게이트 글래스(AsSG), 붕소인 실리게이트 글래스(BPSG) 및 인실리게이트 글래스(PSG)로 구성된 그룹중에서 하나인 것을 특징으로 하는 반도체장치.
  3. 청구범위 제1항에 있어서, 비트라인이 텅스텐 실리사이드, 몰리브덴 실리사이드, 타이타늄 실리사이드로 구성된 그룹중에서 하나인 것을 특징으로 하는 반도체장치.
  4. (a) 공지의 방법에 의해 p형 실리콘기판(1)상에 n형 접합층(2)과 폴리실리콘 게이트 전극(3), 및 게이트 산화막(4)을 형성하는 공정. (b) 상기 게이트 산화막(4)상에 도우프트 글래스(doped glass)막(5)을 형성시키는 공정. (c)상기 도우프트 글래스막(5)상에 비트라인층(6)을 화학적 기상증착법에 의해 형성하는 공정. (d) 상기 비트라인층(6)상에 플라즈마 옥시 나이트라이드막(7)을 형성하는 공정. (e) 상기 플라즈마 옥시 나이트라이드막(7)상에 도우프트 글래스(8)를 형성하는 공정. (f) 상기 도우프트 글래스(8)상에 메탈전극(9)을 형성하는 공정으로 이루어져, 상기 도우프트 글래스막(8)과 식각비율이 동일한 플라즈마 옥시 나이트라이드막(7)을 비트라인층(6)상에 형성하여 컨택식각시 양호한 식각형상을 얻도록 한 것을 특징으로 하느 반도체장치의 제조방법.
  5. 제4항에 있어서, (b) 공정은 도우프트 글래스막(5)이 인과 붕소가 각각 4.5wt%와 3.2wt%로 도우프되도록 구성하고, 상기 도우프트 글래스막(5)의 두께는 화학적 기상증착법에 의해 3500Å 정도로 한 후, 전기로에서 900℃의 질소분위기로 60분간 열처리 하는 공정을 포함하며, (c) 공정은 비트라인층(6)의 두께가 화학적 기상증착법을 이용하여 2500Å 정도되도록 하는 공정을 포함하며, (d) 공정은 플라즈마 옥시 나이트라이드막(7)의 두께가 화학적 기상증착법에 의해 1800Å 되도록 한 후에, 전기로에서 850℃의 질소분위기로 30분간 열처리 하는 공정을 포함하며, (e)의 공정은 도우프트 글래스막(8)이 인과 붕소가 각각 4.5wt%와 3.2wt%로 도우프되도록 구성하고, 상기 도우프트 글래스막(8)의 두께는 화학적 기상증착법에 의해 6000Å 정도로 한 후, 전기로에서 875℃의 질소분위기로 60분간 열처리 하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880012889A 1988-09-30 1988-09-30 반도체장치 및 제조방법 KR910008835B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019880012889A KR910008835B1 (ko) 1988-09-30 1988-09-30 반도체장치 및 제조방법
US07/411,705 US5071790A (en) 1988-09-30 1989-09-25 Semiconductor device and its manufacturing method
JP1252520A JP2918167B2 (ja) 1988-09-30 1989-09-29 半導体装置の製造方法

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KR1019880012889A KR910008835B1 (ko) 1988-09-30 1988-09-30 반도체장치 및 제조방법

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KR910008835B1 KR910008835B1 (ko) 1991-10-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100367499B1 (ko) * 1995-12-29 2003-03-06 주식회사 하이닉스반도체 반도체소자의제조방법

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* Cited by examiner, † Cited by third party
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US6022799A (en) * 1995-06-07 2000-02-08 Advanced Micro Devices, Inc. Methods for making a semiconductor device with improved hot carrier lifetime
US5710067A (en) * 1995-06-07 1998-01-20 Advanced Micro Devices, Inc. Silicon oxime film
US5821172A (en) * 1997-01-06 1998-10-13 Advanced Micro Devices, Inc. Oxynitride GTE dielectrics using NH3 gas
US6235650B1 (en) 1997-12-29 2001-05-22 Vanguard International Semiconductor Corporation Method for improved semiconductor device reliability
US6124217A (en) * 1998-11-25 2000-09-26 Advanced Micro Devices, Inc. In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects
US6265295B1 (en) 1999-09-03 2001-07-24 Taiwan Semiconductor Manufacturing Company Method of preventing tilting over

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US4342617A (en) * 1981-02-23 1982-08-03 Intel Corporation Process for forming opening having tapered sides in a plasma nitride layer
JPS57170550A (en) * 1981-04-15 1982-10-20 Toshiba Corp Manufacture of semiconductor device
JPS5923544A (ja) * 1982-07-30 1984-02-07 Toshiba Corp 半導体装置の製造方法
JPS6081840A (ja) * 1983-10-11 1985-05-09 Nec Corp 半導体装置
JPS60224231A (ja) * 1984-04-20 1985-11-08 Hitachi Ltd 半導体装置
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JPS63261730A (ja) * 1987-04-17 1988-10-28 Sanyo Electric Co Ltd 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100367499B1 (ko) * 1995-12-29 2003-03-06 주식회사 하이닉스반도체 반도체소자의제조방법

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US5071790A (en) 1991-12-10
KR910008835B1 (ko) 1991-10-21
JPH02135759A (ja) 1990-05-24
JP2918167B2 (ja) 1999-07-12

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