KR900002638A - 샘플홀드회로 - Google Patents

샘플홀드회로 Download PDF

Info

Publication number
KR900002638A
KR900002638A KR1019890009712A KR890009712A KR900002638A KR 900002638 A KR900002638 A KR 900002638A KR 1019890009712 A KR1019890009712 A KR 1019890009712A KR 890009712 A KR890009712 A KR 890009712A KR 900002638 A KR900002638 A KR 900002638A
Authority
KR
South Korea
Prior art keywords
stage
gate
hold circuit
shift register
sample hold
Prior art date
Application number
KR1019890009712A
Other languages
English (en)
Other versions
KR920004115B1 (ko
Inventor
노부다카 기타가와
아키히로 스에다
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR900002638A publication Critical patent/KR900002638A/ko
Application granted granted Critical
Publication of KR920004115B1 publication Critical patent/KR920004115B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/66—Transforming electric information into light information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Shift Register Type Memory (AREA)
  • Video Image Reproduction Devices For Color Tv Systems (AREA)

Abstract

내용 없음.

Description

샘플홀드회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1실시예에 따른 샘플홀드회로의 부분회로 구성도.
제 2 도는 제 1 도에 도시된 1실시예에서 n비트시프트레지스터의 각 단을 구성하는 1비트시프트레지스터의 회로도.
제 3 도는 제 1 도에 도시된 1 실시예에서 n비트시프트레지스터의 동작을 도시한 타이밍챠트.
제 4 도는 제 1 도에 도시된 1 실시예에서 각 샘플홀드소자의 홀드전압의 오프셋을 도시한 도면.

Claims (2)

  1. 다수의 샘플홀드소자(2)와, 각 샘플홀드소자의 샘플링시기를 각 단 출력신호에 의해 결정하는 다단시프트레지스터(20)를 구비하면서, 그중 상기 다단시프트레지스터(20)의 의각단이 전단에서 시프트된 신호를 인가받기 위한 입력게이트(21)와, 이 입력게이트(21)에 의해 인가된 신호를 다음단으로 시프트하기 위한 출력게이트(22) 및, 상기 입력게이트(21)에 의해 상기 입출력게이트간(21, 22)에 인가된 신호를 출력하는 수단(23)으로 구성된 것을 특징으로 하는 샘플홀드회로.
  2. 제 1 항에 있어서, 상기 다단시프트레지스터 각 단의 입력게이트(21)와 각 단의 출력게이트(22)는 서로 다른 위상의 클럭(ΦA, ΦA)으로 구동되는 것을 특징으로 하는 샘플홀드회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890009712A 1988-07-07 1989-07-07 샘플홀드회로 KR920004115B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63-169645 1988-07-07
JP63169645A JPH0221499A (ja) 1988-07-07 1988-07-07 サンプルホールド回路
JP88-169645 1988-07-07

Publications (2)

Publication Number Publication Date
KR900002638A true KR900002638A (ko) 1990-02-28
KR920004115B1 KR920004115B1 (ko) 1992-05-25

Family

ID=15890319

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890009712A KR920004115B1 (ko) 1988-07-07 1989-07-07 샘플홀드회로

Country Status (5)

Country Link
US (1) US5016263A (ko)
EP (1) EP0350027B1 (ko)
JP (1) JPH0221499A (ko)
KR (1) KR920004115B1 (ko)
DE (1) DE68918180T2 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4242201A1 (de) * 1992-12-15 1994-06-16 Philips Patentverwaltung Schaltungsanordnung zum Verzögern eines Nutzsignals
JP2827867B2 (ja) * 1993-12-27 1998-11-25 日本電気株式会社 マトリックス表示装置のデータドライバ
TW250607B (en) * 1994-03-17 1995-07-01 Advanced Micro Devices Inc Precoded waveshaping transmitter for twisted pair which eliminates the need for a filter
FR2824177B1 (fr) * 2001-04-26 2004-12-03 Centre Nat Rech Scient Echantillonneur analogique rapide a grande profondeur memoire
KR100574363B1 (ko) * 2002-12-04 2006-04-27 엘지.필립스 엘시디 주식회사 레벨 쉬프터를 내장한 쉬프트 레지스터
FR2872331B1 (fr) * 2004-06-25 2006-10-27 Centre Nat Rech Scient Cnrse Echantillonneur analogique rapide pour enregistrement et lecture continus et systeme de conversion numerique
US7716546B2 (en) * 2007-10-03 2010-05-11 International Business Machines Corporation System and method for improved LBIST power and run time

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2044675A1 (ko) * 1969-05-23 1971-02-26 Sfim
US3657699A (en) * 1970-06-30 1972-04-18 Ibm Multipath encoder-decoder arrangement
US4152606A (en) * 1977-09-16 1979-05-01 Hewlett-Packard Company Waveform capture device
JPS54161288A (en) * 1978-06-12 1979-12-20 Hitachi Ltd Semiconductor device
JPS5540456A (en) * 1978-09-14 1980-03-21 Matsushita Electric Ind Co Ltd Sample holing device
JPH07118794B2 (ja) * 1983-03-16 1995-12-18 シチズン時計株式会社 表示装置
JPS59223998A (ja) * 1983-06-03 1984-12-15 Toshiba Corp 擬似スタテイツクｍｏｓ回路
JPS6143015A (ja) * 1984-08-07 1986-03-01 Toshiba Corp デ−タ遅延記憶回路
US4873671A (en) * 1988-01-28 1989-10-10 National Semiconductor Corporation Sequential read access of serial memories with a user defined starting address

Also Published As

Publication number Publication date
KR920004115B1 (ko) 1992-05-25
JPH0221499A (ja) 1990-01-24
DE68918180D1 (de) 1994-10-20
EP0350027B1 (en) 1994-09-14
US5016263A (en) 1991-05-14
EP0350027A3 (en) 1991-01-02
DE68918180T2 (de) 1995-03-02
JPH0512799B2 (ko) 1993-02-18
EP0350027A2 (en) 1990-01-10

Similar Documents

Publication Publication Date Title
KR0176986B1 (ko) 데이타 구동기
KR880014475A (ko) 반도체 집적회로장치
KR920001420A (ko) 디스플레이 장치용 칼럼 전극 구동회로
KR880009381A (ko) 반도체 집적회로장치
KR900002638A (ko) 샘플홀드회로
DK144187D0 (da) Digitalt signalbehandlingskredsloeb til behandling af digitalsignaler paa seriebitform
KR920003658A (ko) 논리비교회로
KR920001830A (ko) 입력가중형 트랜스 버셜필터
KR910014949A (ko) 시프트 레지스터
JPS6045511B2 (ja) ラッチ付きシフトレジスタ
KR880005603A (ko) 디지탈 뮤팅 회로
KR920009091A (ko) A/d 변환기
KR850002717A (ko) D/a변 환
GB1229349A (ko)
SU1381599A1 (ru) Устройство дл сдвига импульсов
KR900002557A (ko) 배럴시프터
KR920014182A (ko) 동기신호 검출회로
SU1695389A1 (ru) Устройство дл сдвига импульсов
KR910000151Y1 (ko) 콤팩트 디스크 드라이브의 보완된 동기 검출회로
KR930006540A (ko) 승산 회로의 부분 승수 선택 회로
SU1538255A1 (ru) Преобразователь пр мого последовательного кода в дополнительный
KR920019082A (ko) 클럭 전환 회로
SU684710A1 (ru) Фазоимпульсный преобразователь
SU556500A1 (ru) Ячейка пам ти дл сдвигового регистра
SU430371A1 (ru) Датчик случайных чисел

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030430

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee