KR890008947A - 알루미늄-실리콘 합금 배선막과 실리콘 기판간에 오옴접속을 갖는 반도체 메모리장치 - Google Patents

알루미늄-실리콘 합금 배선막과 실리콘 기판간에 오옴접속을 갖는 반도체 메모리장치 Download PDF

Info

Publication number
KR890008947A
KR890008947A KR1019880014452A KR880014452A KR890008947A KR 890008947 A KR890008947 A KR 890008947A KR 1019880014452 A KR1019880014452 A KR 1019880014452A KR 880014452 A KR880014452 A KR 880014452A KR 890008947 A KR890008947 A KR 890008947A
Authority
KR
South Korea
Prior art keywords
film
memory device
insulating film
wiring film
semiconductor memory
Prior art date
Application number
KR1019880014452A
Other languages
English (en)
Other versions
KR920007447B1 (en
Inventor
다이지 에마
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR890008947A publication Critical patent/KR890008947A/ko
Application granted granted Critical
Publication of KR920007447B1 publication Critical patent/KR920007447B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

알루미늄-실리콘 합급 배선막과 실리콘 기판간에 오옴접속을 갖는 반도체 메모리장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도는 본 발명의 바람직한 실시예의 반도체 메모리장치의 평면도,
제3A도는 바람직한 실시예의 반도체 메모리장치의 주변회로부분의 층구조를 도시한 단면도,
제3B도는 바람직한 실시예의 반도체 메모리장치의 메모리 셀 부분의 층구조를 도시한 단면도,
제 4 도는 제3B도의 단면에 대해 직각 방향으로 취한 층구조의 부분의 단면도.

Claims (10)

  1. 실리콘 기판상에 제공되는 메모리셀 부분 및 주변회로 부분으로 구성되며. 메모리 셀 부분은 실리콘 기판상에 형성되는 제1절연막 및 제1절연막 상에 형성되며 차례로 스택된 폴리실리콘막 및 금속실리사이드막을 포함하는 제1배선막으로 구성되며, 주변회로부분은 실리콘 기판상에 형성되는 접속호울을 갖는 제2절연막 제1의 배선막의 것과 동일하며, 제1배선막의 형성과 동시에 형성되는 층구조를 갖는 접속호울에 형성된 장벽층 및 접속호울에서 장벽층을 덮는 알루미늄 및 실리콘의 합금의 제2배선막으로 구성되는 것을 특징으로 하는 반도체 메모리장치.
  2. 제1항에 있어서, 메모리 셀 부분은 다수의 메모리 셀을 포함하는 메모리 셀 어레이로 구성되는 것을 특징으로 하는 반도체 메모리장치.
  3. 제2항에 있어서, 주변회로부분은 메모리 셀 어레이에서 판독된 정보신호를 증폭하기 위한 센스증폭기 수단, 외부 회로에서 공급된 어드레스 신호를 디코딩하기 위한 어드레스 디코더 수단, 및 센스 증폭기수단에서 공급되거나 디코더수단에 공급된 신호에 대해 논리동작을 수행하기 위한 논리수단으로 구성된 것을 특징으로 하는 반도체 메모리장치.
  4. 제1항에 있어서, 제1배선막 및 장벽층의 각각에 포함된 금속 실리사이드막은 내화성 금속실리사이드로 구성되는 것을 특징으로 하는 반도체 메모리장치.
  5. 제4항에 있어서, 금속 실리사이드막은 텅스텐 실리사이드 몰리브덴 실리사이드, 탄탈실리사이드 및 티타늄 실리사이드로 구성된 그룹에서 선택된 재료로 구성되는 것을 특징으로 하는 반도체 메모리장치.
  6. 제1항에 있어서, 제1배선막 및 장벽층의 각각에 포함된 폴리실리콘막은 n형 불순물로 도우프되는 것을 특징으로 하는 반도체 메모리장치.
  7. 제1항에 있어서, 반도체 메모리장치는 다이나믹 랜덤 억세스 메모리장치이며, 제1배선막은 다이나믹 랜덤 억세스 메모리장치의 비트선인 것을 특징으로 하는 반도체 메모리장치.
  8. 제1항에 있어서, 제2배선막이 형성된 것 상에 형성된 제3절연막으로 더 구성되며, 제3절연막은 장벽층이 노출되는 통구를 가지며, 제2배선막은 통구에서 장벽층을 덮으며, 제3절연막도 역시 제1배선막을 덮는 것을 특징으로 하는 반도체 메모리장치.
  9. 실리콘 기판상에 구비되는 메모리 셀 부분과 주변회로 부분으로 구성되며, 메모리 셀 부분은 기판상에 형성된 제1필드 절연막; 실리콘기판 및 제1필드 절연막상에 형성된 제1절연막 및 제1절연막상에 형성되며, 차례로 스택된 폴리실리콘막 및 금속 실리사이드막을 포함하는 제1배선막으로 구성되며, 주변회로 부분은 기판 및 제2절연막상에 형성되 제2필드 절연막; 실리콘 기판상에 형성된 접속호울을 갖는 제2절연막; 제1배선막의 것과 동일하며, 제1배선막의 형성과 동시에 형성되는 층구조를 갖는 접속호울에 형성된 장벽층 및 접속호울에서 장벽층을 덮는 알루미늄 및 실리콘의 합금의 제2배선막으로 구성되며, 제1방향으로 연장되는 접속호울의 에지는 제2필드절연막의 에지에 의해 정의되며, 제2방향으로 연장되는 접속호울의 에지는 제2절연막을 패턴화함에 의하여 정의되는 것을 특징으로 하는 반도체 메모리장치.
  10. 제1항에 있어서, 제2방향은 제2배선막이 연장되는 방향과 동일방향이며, 제1방향은 제2방향에 대해 수직인 것을 특징으로 하는 반도체 메모리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8814452A 1987-11-05 1988-11-03 Semiconductor memory device having an ohmic contact between an aluminium-silicon alloy metalization film ad a silicon substrate KR920007447B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62278286A JP2548957B2 (ja) 1987-11-05 1987-11-05 半導体記憶装置の製造方法
JP?62-278286 1987-11-05

Publications (2)

Publication Number Publication Date
KR890008947A true KR890008947A (ko) 1989-07-13
KR920007447B1 KR920007447B1 (en) 1992-09-01

Family

ID=17595230

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8814452A KR920007447B1 (en) 1987-11-05 1988-11-03 Semiconductor memory device having an ohmic contact between an aluminium-silicon alloy metalization film ad a silicon substrate

Country Status (4)

Country Link
US (1) US4931845A (ko)
EP (1) EP0315422A3 (ko)
JP (1) JP2548957B2 (ko)
KR (1) KR920007447B1 (ko)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247197A (en) * 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
KR920010695B1 (ko) * 1989-05-19 1992-12-12 삼성전자 주식회사 디램셀 및 그 제조방법
US5281838A (en) * 1990-03-13 1994-01-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having contact between wiring layer and impurity region
JP2623019B2 (ja) * 1990-03-13 1997-06-25 三菱電機株式会社 半導体装置
DE4113733C2 (de) * 1990-04-27 1996-01-25 Mitsubishi Electric Corp Feldeffekttransistor, Verfahren zur Herstellung derselben und DRAM unter Verwendung desselben
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
DE4143389C2 (de) * 1990-04-27 1994-11-24 Mitsubishi Electric Corp Verfahren zum Herstellen eines DRAM
JP2524862B2 (ja) * 1990-05-01 1996-08-14 三菱電機株式会社 半導体記憶装置およびその製造方法
JPH0449654A (ja) * 1990-06-19 1992-02-19 Nec Corp 半導体メモリ
GB2252667A (en) * 1990-10-08 1992-08-12 Gold Star Electronics Contact in DRAM device
NL9100039A (nl) * 1991-01-11 1992-08-03 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van de halfgeleiderinrichting.
JPH0575061A (ja) * 1991-09-13 1993-03-26 Oki Electric Ind Co Ltd 半導体記憶装置の配線構造
JPH05110005A (ja) * 1991-10-16 1993-04-30 N M B Semiconductor:Kk Ｍｏｓ型トランジスタ半導体装置およびその製造方法
KR960005248B1 (ko) * 1991-10-24 1996-04-23 마쯔시다덴기산교 가부시기가이샤 반도체기억장치 및 그 제조방법
JP2748070B2 (ja) * 1992-05-20 1998-05-06 三菱電機株式会社 半導体装置およびその製造方法
JP3413876B2 (ja) * 1992-07-08 2003-06-09 セイコーエプソン株式会社 半導体装置
JP3013624B2 (ja) * 1992-09-01 2000-02-28 日本電気株式会社 半導体集積回路装置
KR960006693B1 (ko) * 1992-11-24 1996-05-22 현대전자산업주식회사 고집적 반도체 접속장치 및 그 제조방법
US5545926A (en) 1993-10-12 1996-08-13 Kabushiki Kaisha Toshiba Integrated mosfet device with low resistance peripheral diffusion region contacts and low PN-junction failure memory diffusion contacts
US6057604A (en) * 1993-12-17 2000-05-02 Stmicroelectronics, Inc. Integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure
JP3326267B2 (ja) * 1994-03-01 2002-09-17 三菱電機株式会社 半導体装置およびその製造方法
US6025264A (en) * 1998-02-09 2000-02-15 United Microelectronics Corp. Fabricating method of a barrier layer
KR100553682B1 (ko) * 2003-03-07 2006-02-24 삼성전자주식회사 게이트 전극을 갖는 반도체 소자 및 그 형성방법
US7205665B1 (en) * 2005-10-03 2007-04-17 Neah Power Systems, Inc. Porous silicon undercut etching deterrent masks and related methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4042953A (en) * 1973-08-01 1977-08-16 Micro Power Systems, Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS5893347A (ja) * 1981-11-30 1983-06-03 Toshiba Corp Ｍｏｓ型半導体装置及びその製造方法
US4569122A (en) * 1983-03-09 1986-02-11 Advanced Micro Devices, Inc. Method of forming a low resistance quasi-buried contact
JPS6066465A (ja) * 1983-09-21 1985-04-16 Seiko Epson Corp 半導体装置
JPS6079746A (ja) * 1983-10-07 1985-05-07 Hitachi Ltd 半導体装置及びその機能変更方法
JPH0763060B2 (ja) * 1984-03-15 1995-07-05 松下電器産業株式会社 半導体装置の製造方法
JPH0789569B2 (ja) * 1986-03-26 1995-09-27 株式会社日立製作所 半導体集積回路装置及びその製造方法

Also Published As

Publication number Publication date
EP0315422A3 (en) 1990-11-14
JPH01120863A (ja) 1989-05-12
JP2548957B2 (ja) 1996-10-30
US4931845A (en) 1990-06-05
EP0315422A2 (en) 1989-05-10
KR920007447B1 (en) 1992-09-01

Similar Documents

Publication Publication Date Title
KR890008947A (ko) 알루미늄-실리콘 합금 배선막과 실리콘 기판간에 오옴접속을 갖는 반도체 메모리장치
JP2588732B2 (ja) 半導体記憶装置
JPS6114747A (ja) メモリ
KR960032759A (ko) 메모리 장치
US5815428A (en) Semiconductor memory device having hierarchical bit line structure
KR910020904A (ko) 반도체기억장치 및 그 제조 방법
KR890016573A (ko) 반도체기억장치
KR850006983A (ko) 반도체 메모리 장치
KR840003146A (ko) 다이나믹(Dynamic) RAM 집적회로 장치
KR940008099A (ko) 적층 캐패시터 셀을 갖는 반도체 메모리
KR900017187A (ko) 반도체 기억장치
KR950021666A (ko) 반도체 장치
US5455787A (en) Semiconductor memory device
JPH10163346A (ja) 半導体メモリのパワーライン配線構造
JP3241244B2 (ja) 半導体記憶装置
KR980006297A (ko) 다중 레벨 도전체 워드라인 스트래핑 방법
US5747843A (en) Semiconductor memory device
US5644527A (en) Semiconductor memory device
KR940007876A (ko) 폴디드 비트라인 방식의 디램쎌 어레이
EP0942432A3 (en) Non-volatile semiconductor storage device
KR980006298A (ko) 정합 지연 워드선 스트랩
JP2871040B2 (ja) 半導体記憶装置
JPS60189253A (ja) スタテイツク型半導体記憶装置
JP2743459B2 (ja) 半導体記憶装置
JPH0127518B2 (ko)

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030825

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee