KR890007381A - 반도체소자 및 그 제조방법 - Google Patents

반도체소자 및 그 제조방법 Download PDF

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KR890007381A
KR890007381A KR1019880013475A KR880013475A KR890007381A KR 890007381 A KR890007381 A KR 890007381A KR 1019880013475 A KR1019880013475 A KR 1019880013475A KR 880013475 A KR880013475 A KR 880013475A KR 890007381 A KR890007381 A KR 890007381A
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South Korea
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masking layer
semiconductor substrate
main surface
range
doping
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KR1019880013475A
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English (en)
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크리스티앙 씨 아빠스
페터 로그빌러
잔 보보릴
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원본미기재
비비씨 브라운 보버리 에이쥐
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Publication of KR890007381A publication Critical patent/KR890007381A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Abstract

내용 없음

Description

반도체소자 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 보호영역을 가진 반도체 소자를 통한 축상 단면도.
제2a도는 선형으로 감소하는 도우핑 밀도를 가진 본 발명에 따른 보호영역의 도우핑 밀도를 나타낸 도면.
제2b도는 제2a도에 따른 해당하는 반도체 소자를 통한 축상 단면의 세부도.
제3a도는 두 개의 단차를 갖는 본 발명에 따른 보호영역의 도우핑 밀도를 나타낸 도면.
제3b도는 제3a도에 따른 해당 반도체 소자를 통한 축상 단면도의 세부도

Claims (10)

  1. 반도체기판(1)의 내측으로 연장되고 반도체기판(1)의 주표면(2)으로부터 내부로 연장된 옆으로 접경된, 높게 도우프된 영역(3)과 이 높게 도우프된 영역(3)을 둘러 싼 살짝 도우프된 영역으로 형성되며 높게 도우프된 영역(3)의 모서리에 있는 반도체기판(1)의 주표면(2)에서 나타나는 하나 이상의 pn접합(5)을 포함하며, 높게 도우프된 영역의 모서리는 도우핑 밀도가 높게 도우프된 영역(3)으로부터 pn 접합 (5) 쪽으로 주표면(2)에 평행한 방향에서 점차 감소하는 보호영역(6a,6b)에 의해 형성되는 반도체소자에 있어서, 보호영역(6a,6b)은 높게 도우프된 영역(3)근처에서 최대 관통깊이를 가지며 보호영역(6a,6b)의 최대 관통 깊이는 인접한 높게 도우프된 영역(3)의 관통 깊이보다 더 큰 반도체소자.
  2. 제1항에 있어서, 보호영역(6a,6b)이 1015㎝-3를 넘지 않는 최대 도우핑 밀도를 가지며 보호영역(6a,6b)이 살짝 도우프된 영역의 두께(d)에 견줄만한 폭(b)를 가지며 보호영역(6a,6b)이 최대 관통 깊이가 40㎛ 이상80㎛ 이하인 반도체소자.관통 깊이보다 더 큰 반도체소자.
  3. 제2항에 있어서, 보호영역(6a,6b)의 도우핑 밀도가 주표면(2)에 평행한 방향에서 선형적으로 감소하는 반도체소자.
  4. 제2항에 있어서, 보호영역(6a,6b)의 도우핑 밀도가 적어도 두개 이상으로 형성된 주표면(2)에 평행한 방향에서 선형적으로 감소하는 반도체소자.
  5. 제4항에 있어서, 보호영역(6a,6b)에 정밀한 두개의 계단이 형성되며 2차 계단(8)의 도우핑 밀도가 높게 도우프된 영역(3)에 인접한 1차 계단(7)의 도우핑 밀도의 약 반정도인 반도체소자.
  6. 반도체기판(1)의 주표면(2)이 보호영역(6a,6b)의 범위에서 V자형 마스킹층으로 덮이며, 도우핑 원자는 주어진 에너지로 혼입되어 V자형 마스킹층(9)이 그의 무딘 단부에서 반도체기판(1)내로 도우핑 원자가 뚫고 들어가지 못하게 하며 마스킹층(9)은 연속 확산 처리 전에 제거되는 제3항에 기재된 반도체소자의 제조방법.
  7. 반도체기판(1)의 주표면(2)이 보호영역(6a,6b)의 범위에서 V자형 마스킹층으로 덮이고 도우핑 원자는 주어진 에너지로 혼입되어 V자형 마스킹층(9)이 그의 무딘 단부에서 반도체기판(1)내로 도우핑 원자가 뚫고 들어가지 못하게 하며 V자형 마스킹층(9)은 연속 확산 처리에서 확산원(11)으로 사용되는 제3항에 기재된 반도체소자의 제조방법.
  8. 도우핑 원자의 1차 혼입에서, 반도체기판(1)의 주표면(2)은 2차 계단(8)의 범위에 마스킹층(9)이 없으며, 계속되는 도우핑 원자의 2차 혼입에서, 주표면(2)은 전 보호영역(6a,6b)의 범위에서 마스킹층(9)이 없는 제5항에 기재된 반도체소자의 제조방법.
  9. 반도체기판(1)의 주표면(2)이 2차 계단(8)의 범위에서 마스킹층(9)에 의해 덮이며 도우핑 원자는 주어진 고에너지로 혼입되어 도우핑 원자가 2차 계단(8)의 범위에서도 반도체기판(1)의 마스킹층(9)을 관통하며 도우핑 원자는 주어진 저에너지로 혼입되어 도우핑 원자가 2차 계단(8)범위에서도 반도체기판(1)의 마스킹층(9)을 관통하지 않는 제5항에 기재한 반도체소자의 제조방법.
  10. 도우핑 원자의 혼입 도중 반도체기판(1)의 주표면(2)이 2차 계단(8)의 범위에서 마스킹층(9)으로 덮이며, 마스킹층(9)은 연속 확산 처리 도중 2차 계단(8)의 범위에서 확산원(11)으로 사용되는 제5항에 기재한 반도체소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880013475A 1987-10-15 1988-10-15 반도체소자 및 그 제조방법 KR890007381A (ko)

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CH4050/87-1 1987-10-15

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US (1) US5093693A (ko)
EP (1) EP0311816A1 (ko)
JP (1) JPH01140767A (ko)
KR (1) KR890007381A (ko)
CN (1) CN1034288A (ko)

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CN1034288A (zh) 1989-07-26
US5093693A (en) 1992-03-03
JPH01140767A (ja) 1989-06-01
EP0311816A1 (de) 1989-04-19

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