KR900005556A - 반도체 장치 제조방법 - Google Patents

반도체 장치 제조방법 Download PDF

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KR900005556A
KR900005556A KR1019890006608A KR890006608A KR900005556A KR 900005556 A KR900005556 A KR 900005556A KR 1019890006608 A KR1019890006608 A KR 1019890006608A KR 890006608 A KR890006608 A KR 890006608A KR 900005556 A KR900005556 A KR 900005556A
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type dopant
implantation
semiconductor device
silicon body
manufacturing
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KR1019890006608A
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KR0158873B1 (ko
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스톨마이에르 안드레
마리아 데오도루스 마테우스 반 아테쿰 파울루스
요하네스 덴 블란켄 후베르투스
안토니우스 반 데르 플라스 파울루스
데 베르도트 라이니에르
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이반 밀러 레르너
엔.브이.필립스 글로아이람펜파브리켄
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/919—Compensation doping

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체 장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1 내지 5도는 본 발명에 따른 방법으로 실현된 반도체 장치의 제조단계를 도시한 개략도.

Claims (8)

  1. 필드 산화물 영역에 의해 서로 절연되며 실리콘 바디의 표면에 인접하며, 필드 산화물 영역 형성후에 n형 도펀트 및 p형 도펀트로의 주입에 의해 형성되어지는 다수의 반도체 영역이 존재하는 실리콘 바디를 구비한 반도체 장치 제조방법에 있어서, 반도체 영역을 형성하기 위하여, 형성되어질 반도체 영역의 일부 영역에서 생성된 창을 통해 실행되는 n형 도펀트 주입이 주입 마스크를 사용하지 않고 실행된 p형 도펀트 주입과 결합되는 것을 특징으로 하는 반도체장치 제조방법
  2. 제1항에 있어서, 반도체 영역을 형성하기 위하여 n형 도펀트 주입은 p형 도펀트 주입과 결합되며, 이 p형 도펀트 주입은 상기 두가지 주입이 실리콘 바디의 동일 깊이에서 최대 도핑 농도를 나타낼 정도의 에너지를 사용하여 실행되는 것을 특징으로 하는 반도체 장치 제조방법
  3. 제2항에 있어서, n형 도펀트 주입은 p형 도펀트 주입의 도우즈나 많은 도우즈로 실행되는 것을 특징으로 하는 반도체 장치 제조방법
  4. 제2항에 있어서, n형 도펀트 주입은 p형 도펀트 주입의 도우즈보다 적은 도우즈로 실행되며, 결합되어질 두 주입은 실리콘 바디의 표면상에서 p형 도펀트가 n형 도펀트의 농도보다 높은 농도를 갖는 정도의 에너지로 실행되는 것을 특징으로 하는 반도체 장치 제조방법.
  5. 제2항에 있어서, 반도체 영역을 형성하기 위하여 n형 도펀트 주입은 n형 도펀트 주입의 실리콘 바디 깊이와 동일한 깊이에서 최대 도핑 농도를 갖는 p형 도펀트로의 제 1주입뿐만 아니라, 제1주입의 에너지보다 낮은 에너지와 실리콘 바디의 표면상에서 p형 도펀트가 n형 도펀트로의 농도보다 높은 농도를 갖는 정도의 도우즈로 실행된 p형 도펀트로의 제2주입과도 결합되는 것을 특징으로 하는 반도체 장치 제조방법.
  6. 제4 또는 5항에 있어서, 실리콘 바디의 표면상에서 p형 도펀트가 n형 도펀트의 농도보다 높은 농도를 나타내는 정도의 도우즈 및 에너지로 실행된 p형 도펀트 주입은 실리콘 바디의 표면에 게이트 산화물층이 제공된 후에만 수행되는 것을 특징으로 하는 반도체 장치 제조방법
  7. 제6항에 있어서, n형 도펀트 주입은 실리콘 바디의 표면에 게이트 산화물층이 제공되기전에 실행되는 것을 특징으로 하는 반도체 장치 제조방법.
  8. 선행된 항중 어느 한 항에 있이서. n형 도펀트로서 인이 사용되며 p형 도펀트로서 붕소가 사용된 것을특징으로 하는 반도체 장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890006608A 1988-09-09 1989-05-18 반도체 디바이스 제조방법 KR0158873B1 (ko)

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NL8802219A NL8802219A (nl) 1988-09-09 1988-09-09 Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
NL8802219 1988-09-09

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US (1) US5384279A (ko)
EP (1) EP0358246B1 (ko)
JP (1) JP2578204B2 (ko)
KR (1) KR0158873B1 (ko)
DE (1) DE68926985T2 (ko)
NL (1) NL8802219A (ko)

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EP0358246A1 (en) 1990-03-14
US5384279A (en) 1995-01-24
EP0358246B1 (en) 1996-08-21
KR0158873B1 (ko) 1999-02-01
JPH0283966A (ja) 1990-03-26
DE68926985D1 (de) 1996-09-26
DE68926985T2 (de) 1997-03-06
NL8802219A (nl) 1990-04-02
JP2578204B2 (ja) 1997-02-05

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