KR890001200A - 파워 모스 트랜지스터 구조 - Google Patents
파워 모스 트랜지스터 구조 Download PDFInfo
- Publication number
- KR890001200A KR890001200A KR1019880007239A KR880007239A KR890001200A KR 890001200 A KR890001200 A KR 890001200A KR 1019880007239 A KR1019880007239 A KR 1019880007239A KR 880007239 A KR880007239 A KR 880007239A KR 890001200 A KR890001200 A KR 890001200A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- drain
- source
- connection layer
- mos transistor
- Prior art date
Links
- 230000000295 complement effect Effects 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 238000007747 plating Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 150000003377 silicon compounds Chemical class 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1D도는 본 발명의 장정들을 강조하는 상태도.
제2A도 내지 제2C도는 본 발명에 따른 제1,제2, 및 제3접속 레벨의 평면도.
제3도는 본 발명에 특히 적합한 N채널 DMOS 트랜지스터 구조의 단면도.
Claims (5)
- 동일한 기판면에서 게이트 접촉영역, 소스접촉 영역, 드레인 접속영역 및 세 접속층 레벨로 구성되고, 제1접속층레벨(20)은 모든 게이트들과 접촉을 이루고 각 게이트와 인접한 게이트 사이의 접속을 이루며, 이 제1접속층은 소스 접촉영역 및 드레인 접촉영역 상부의 개구부로 구성되는 병렬파워 모수 트랜지스터 구조에 있어서, 소스 접촉 영역 및 드레인 접촉영역 상부에서 개방된 제1분리층과, 모든 소스 영역(22) 및 드레인 영역(23)과 접촉을 이루고 각 소스, (혹은 드레인)영역 및 인접한 소스(혹은 드레인) 영역간의 접속을 이루며 각 드레인(혹은 소스) 접점을 분리시키는 개구부를 포함하는 제2접속층 레벨과, 드레인 영역 혹은 소스영역 위에서 개방된 제2분리층과, 제2접속층 레벨의 모든 드레인 영역 혹은 소스영역과 접촉을 이루는 제3연속접속층 레벨(25)이 추가로 구성됨이 특정인 병렬 파워 모스 트랜지스터 구조.
- 제1항에 있어서, 제1접속층 레벨은 다결정 실리콘 및 규소화합물로 구성되고, 제2 및 제3접속층 레벨은 금속도금층으로 구성됨이 특징인 모스 트랜지스터 구조.
- 각 트랜지스터는 제1항에 따른 구조로 이루어지고, 제1형태의 모스 트랜지스터에서 제2접속층은 소스와 결합되며, 제2형태의 모스 트랜지스터에서 제2접속층은 드레인과 접속됨이 특징인 상보 모스 트랜지스터 구조.
- 제3항에 있어서, DMOS형 측방향 N채널 트랜지스터 및 확장 드레인형 측방향 P채널 트랜지스터로 구성되고 N채널 DOMS의 채널영역(33)은 전계 산화물층(40)에 의하여 드레인 영역(35)으로부터 분리되고, POMS의 드레인 확장 영역(61)은 전계 산화물 영역(60) 아래에서 형성됨이 특징인 모놀리식 집적회로 형태의 상보 모스 트랜지스터(CMOS)구조.
- 제4항에 있어서, PMOS의 드레인 확장 영역(61)의 도우핑은 전계 산화물 영역(60)을 성장시키기 전에 자동 배열되는 방법으로 수행된 결과임이 특징인 상보 모스 트랜지스터 구조.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR87/09157 | 1987-06-22 | ||
FR8709157A FR2616966B1 (fr) | 1987-06-22 | 1987-06-22 | Structure de transistors mos de puissance |
Publications (1)
Publication Number | Publication Date |
---|---|
KR890001200A true KR890001200A (ko) | 1989-03-18 |
Family
ID=9352634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880007239A KR890001200A (ko) | 1987-06-22 | 1988-06-16 | 파워 모스 트랜지스터 구조 |
Country Status (6)
Country | Link |
---|---|
US (1) | US4890142A (ko) |
EP (1) | EP0296997B1 (ko) |
JP (1) | JP2842871B2 (ko) |
KR (1) | KR890001200A (ko) |
DE (1) | DE3873839T2 (ko) |
FR (1) | FR2616966B1 (ko) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4998151A (en) * | 1989-04-13 | 1991-03-05 | General Electric Company | Power field effect devices having small cell size and low contact resistance |
USRE37424E1 (en) * | 1989-06-14 | 2001-10-30 | Stmicroelectronics S.R.L. | Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage |
US5192989A (en) * | 1989-11-28 | 1993-03-09 | Nissan Motor Co., Ltd. | Lateral dmos fet device with reduced on resistance |
JP2858404B2 (ja) * | 1990-06-08 | 1999-02-17 | 株式会社デンソー | 絶縁ゲート型バイポーラトランジスタおよびその製造方法 |
IT1252625B (it) * | 1991-12-05 | 1995-06-19 | Cons Ric Microelettronica | Processo di fabbricazione di transistors a effetto di campo con gate isolato (igfet) a bassa densita' di corto circuiti tra gate e source e dispositivi con esso ottenuti |
US5306652A (en) * | 1991-12-30 | 1994-04-26 | Texas Instruments Incorporated | Lateral double diffused insulated gate field effect transistor fabrication process |
JP3158738B2 (ja) * | 1992-08-17 | 2001-04-23 | 富士電機株式会社 | 高耐圧mis電界効果トランジスタおよび半導体集積回路 |
US5283454A (en) * | 1992-09-11 | 1994-02-01 | Motorola, Inc. | Semiconductor device including very low sheet resistivity buried layer |
US5631177A (en) * | 1992-12-07 | 1997-05-20 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated circuit with power field effect transistors |
US5382536A (en) * | 1993-03-15 | 1995-01-17 | Texas Instruments Incorporated | Method of fabricating lateral DMOS structure |
US5369045A (en) * | 1993-07-01 | 1994-11-29 | Texas Instruments Incorporated | Method for forming a self-aligned lateral DMOS transistor |
DE69321966T2 (de) * | 1993-12-24 | 1999-06-02 | Cons Ric Microelettronica | Leistungs-Halbleiterbauelement |
US5798287A (en) * | 1993-12-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Method for forming a power MOS device chip |
DE69321965T2 (de) * | 1993-12-24 | 1999-06-02 | Cons Ric Microelettronica | MOS-Leistungs-Chip-Typ und Packungszusammenbau |
JP3136885B2 (ja) * | 1994-02-02 | 2001-02-19 | 日産自動車株式会社 | パワーmosfet |
DE59504562D1 (de) * | 1994-03-04 | 1999-01-28 | Siemens Ag | Mis-struktur auf siliciumcarbid-basis mit hoher latch-up-festigkeit |
JP3355817B2 (ja) * | 1994-10-20 | 2002-12-09 | 株式会社デンソー | 半導体装置 |
US6150722A (en) * | 1994-11-02 | 2000-11-21 | Texas Instruments Incorporated | Ldmos transistor with thick copper interconnect |
KR100468342B1 (ko) * | 1996-05-15 | 2005-06-02 | 텍사스 인스트루먼츠 인코포레이티드 | 자기-정렬resurf영역을가진ldmos장치및그제조방법 |
US6140702A (en) * | 1996-05-31 | 2000-10-31 | Texas Instruments Incorporated | Plastic encapsulation for integrated circuits having plated copper top surface level interconnect |
JP3327135B2 (ja) * | 1996-09-09 | 2002-09-24 | 日産自動車株式会社 | 電界効果トランジスタ |
US6140150A (en) * | 1997-05-28 | 2000-10-31 | Texas Instruments Incorporated | Plastic encapsulation for integrated circuits having plated copper top surface level interconnect |
JP3395603B2 (ja) * | 1997-09-26 | 2003-04-14 | 株式会社豊田中央研究所 | 横型mos素子を含む半導体装置 |
US6531355B2 (en) | 1999-01-25 | 2003-03-11 | Texas Instruments Incorporated | LDMOS device with self-aligned RESURF region and method of fabrication |
DE10104274C5 (de) * | 2000-02-04 | 2008-05-29 | International Rectifier Corp., El Segundo | Halbleiterbauteil mit MOS-Gatesteuerung und mit einer Kontaktstruktur sowie Verfahren zu seiner Herstellung |
US6653708B2 (en) | 2000-08-08 | 2003-11-25 | Intersil Americas Inc. | Complementary metal oxide semiconductor with improved single event performance |
JP2004079988A (ja) * | 2002-06-19 | 2004-03-11 | Toshiba Corp | 半導体装置 |
KR100932363B1 (ko) * | 2005-08-10 | 2009-12-16 | 엔엑스피 비 브이 | Ldmos 트랜지스터 |
JP2007273689A (ja) * | 2006-03-31 | 2007-10-18 | Denso Corp | 半導体装置 |
US8169081B1 (en) | 2007-12-27 | 2012-05-01 | Volterra Semiconductor Corporation | Conductive routings in integrated circuits using under bump metallization |
US8084821B2 (en) * | 2008-01-30 | 2011-12-27 | Infineon Technologies Ag | Integrated circuit including a power MOS transistor |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5193878A (ko) * | 1975-02-17 | 1976-08-17 | ||
DE3046749C2 (de) * | 1979-12-10 | 1986-01-16 | Sharp K.K., Osaka | MOS-Transistor für hohe Betriebsspannungen |
JPS57162359A (en) * | 1981-03-30 | 1982-10-06 | Toshiba Corp | Semiconductor device |
GB2098799B (en) * | 1981-05-20 | 1985-08-21 | Nippon Electric Co | Multi-level interconnection system for integrated circuits |
JPS57194567A (en) * | 1981-05-27 | 1982-11-30 | Hitachi Ltd | Semiconductor memory device |
JPS58171861A (ja) * | 1982-04-01 | 1983-10-08 | Toshiba Corp | 半導体装置 |
NL8302092A (nl) * | 1983-06-13 | 1985-01-02 | Philips Nv | Halfgeleiderinrichting bevattende een veldeffekttransistor. |
JPS604253A (ja) * | 1983-06-23 | 1985-01-10 | Nec Corp | 半導体集積回路メモリ |
FR2571178B1 (fr) * | 1984-09-28 | 1986-11-21 | Thomson Csf | Structure de circuit integre comportant des transistors cmos a tenue en tension elevee, et son procede de fabrication |
-
1987
- 1987-06-22 FR FR8709157A patent/FR2616966B1/fr not_active Expired
-
1988
- 1988-06-16 KR KR1019880007239A patent/KR890001200A/ko not_active Application Discontinuation
- 1988-06-17 US US07/208,224 patent/US4890142A/en not_active Expired - Lifetime
- 1988-06-20 JP JP63152107A patent/JP2842871B2/ja not_active Expired - Lifetime
- 1988-06-21 EP EP88420206A patent/EP0296997B1/fr not_active Expired - Lifetime
- 1988-06-21 DE DE8888420206T patent/DE3873839T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0296997A1 (fr) | 1988-12-28 |
FR2616966A1 (fr) | 1988-12-23 |
JP2842871B2 (ja) | 1999-01-06 |
US4890142A (en) | 1989-12-26 |
DE3873839T2 (de) | 1993-05-13 |
JPS6420666A (en) | 1989-01-24 |
EP0296997B1 (fr) | 1992-08-19 |
DE3873839D1 (de) | 1992-09-24 |
FR2616966B1 (fr) | 1989-10-27 |
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