KR840005278A - 3차원 구조 반도체장치(三次元構造半導體裝置) - Google Patents

3차원 구조 반도체장치(三次元構造半導體裝置) Download PDF

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KR840005278A
KR840005278A KR1019830002677A KR830002677A KR840005278A KR 840005278 A KR840005278 A KR 840005278A KR 1019830002677 A KR1019830002677 A KR 1019830002677A KR 830002677 A KR830002677 A KR 830002677A KR 840005278 A KR840005278 A KR 840005278A
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semiconductor film
impurity
doped region
semiconductor
region formed
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KR1019830002677A
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KR900004724B1 (ko
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마사노부 미야오 (외 8)
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미쓰다 가쓰시게
가부시기 가이시 히다찌 세이사꾸쇼
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Publication of KR840005278A publication Critical patent/KR840005278A/ko
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Publication of KR900004724B1 publication Critical patent/KR900004724B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76272—Vertical isolation by lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

3차원 구조 반도체 장치(三次元構造半導體裝置)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 구성을 설명하기 위한 모식도.
제2a도, 제2b도, 제3a도 제3b도 및 제4a도, 제4b도는 각각 본 발명의 상위한 실시예를 도시한 단면도 및 회로도이다.

Claims (7)

  1. 반도체 기판상에 서로 교대로 적층하여 형성된, 각각 적어도 1층의 절연만과 단결정 반도체막을상기 단결정 반도체 막내에 형성된 적어도 1개의 저저항의 불순물 도우프 영역을 갖추고, 상기 불순물 도우프 영역을 게이트, 소오스 또는 드레인으로 하는 다수개의 MOS 트랜지스터가 형성되어 있는 3차원 구조 반도체 장치.
  2. 특허청구의 범위 제1항에 있어서, 상기 반도체 기판의 표면 영역에도, 또 적어도 1개 이상의 불순물 도우프 영역이 형성되어 있는 것을 특징으로 하는 3차원 구조 반도체 장치.
  3. 특허청구의 범위 제1항 또는 제2항에 있어서, 상기 반도체 막내에 형성되어 있는 상기 불순물 도우프 영역은 상기 MOS 트랜지스터의 게이트이며, 상기 반도체 막의 아래쪽에 상기 절연막을 거쳐서 인접하는 다른 상기 반도체 막 도는 상기 반도체 기판내에 형성되어 있는 상기 불순물 도우프 영역은 상기 MOS 트랜지스터의 소오스 또는 드레인인 것을 특징으로 하는 3차원 구조 반도체 장치.
  4. 특허청구의 범위 제1항 또는 제2항에 있어서, 상기 반도체 막내에 형성되어 있는 상기 불순물 도우프 영역은 상기 MOS 트랜지스터의 게이트이며, 상기 반도체 막의 윗쪽에 상기 절연막을 거쳐서 인접하는 다른 반도체 막내에 형성된 상기 불순물 도우프 영역은 상기 MOS 트랜지스터의 소오스 혹은 드레인이다.
  5. 특허청구의 범위 제2항에 있어서, 상기 반도체 막내에 형성되어 있는 상기 불순물 도우프 영역과 상기 반도체 기판의 표면 영역내에 형성된 상기 불순물 도우프 영역과 부분적으로 접속되어 있다.
  6. 특허청구의 범위 제2항에 있어서, 상기반도체 막내에 형성되어 있는 상기 불순물 도우프 영역과 상기 반도체 기판내에 형성되어 있는 상기 불순물 도우프 영역은 분리되어 있다.
  7. 특허청구의 범위 제1항 또는 제2항에 있어서, 최상부에 형성되어 있는 상기 게이트는 불순물이 도우프된 다결정 실리콘 또는 금속으로 된다.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830002677A 1982-06-22 1983-06-16 3차원 구조 반도체 장치(三次元構造半導體裝置) KR900004724B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP57106225A JPH0636423B2 (ja) 1982-06-22 1982-06-22 三次元構造半導体装置
JP106,225 1982-06-22
JP57-106225 1982-06-22

Publications (2)

Publication Number Publication Date
KR840005278A true KR840005278A (ko) 1984-11-05
KR900004724B1 KR900004724B1 (ko) 1990-07-05

Family

ID=14428190

Family Applications (1)

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KR1019830002677A KR900004724B1 (ko) 1982-06-22 1983-06-16 3차원 구조 반도체 장치(三次元構造半導體裝置)

Country Status (5)

Country Link
US (1) US4570175A (ko)
EP (1) EP0097375B1 (ko)
JP (1) JPH0636423B2 (ko)
KR (1) KR900004724B1 (ko)
DE (1) DE3368351D1 (ko)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
KR100510112B1 (ko) * 2000-01-03 2005-08-26 인터내셔널 비지네스 머신즈 코포레이션 다적층 3차원 고밀도 반도체 디바이스 및 그 제조 방법

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JPS6089975A (ja) * 1983-10-24 1985-05-20 Toshiba Corp 半導体装置
CA1237828A (en) * 1984-08-01 1988-06-07 Simon M. Sze Semiconductor-on-insulator (soi) device having electrical short to avoid charge accumulation
EP0191435B1 (en) * 1985-02-13 1990-05-09 Kabushiki Kaisha Toshiba Semiconductor memory cell
JPS61187362A (ja) * 1985-02-15 1986-08-21 Nec Corp 半導体集積回路装置
US4748485A (en) * 1985-03-21 1988-05-31 Hughes Aircraft Company Opposed dual-gate hybrid structure for three-dimensional integrated circuits
US5350933A (en) * 1990-02-21 1994-09-27 Sony Corporation Semiconductor CMOS static RAM with overlapping thin film transistors
US5930608A (en) * 1992-02-21 1999-07-27 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor in which the channel region of the transistor consists of two portions of differing crystallinity
US7391109B2 (en) * 2006-05-22 2008-06-24 Hewlett-Packard Development Company, L.P. Integrated circuit interconnect

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DE1589705A1 (de) * 1967-11-15 1970-04-30 Itt Ind Gmbh Deutsche Mehrere elektrische Funktionsstufen enthaltende integrierte Schaltung
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100510112B1 (ko) * 2000-01-03 2005-08-26 인터내셔널 비지네스 머신즈 코포레이션 다적층 3차원 고밀도 반도체 디바이스 및 그 제조 방법

Also Published As

Publication number Publication date
JPH0636423B2 (ja) 1994-05-11
US4570175A (en) 1986-02-11
JPS58223359A (ja) 1983-12-24
EP0097375A1 (en) 1984-01-04
KR900004724B1 (ko) 1990-07-05
DE3368351D1 (en) 1987-01-22
EP0097375B1 (en) 1986-12-10

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