KR880700454A - 반도체 장치 및 그 제작 공정 - Google Patents

반도체 장치 및 그 제작 공정

Info

Publication number
KR880700454A
KR880700454A KR860700919A KR860700919A KR880700454A KR 880700454 A KR880700454 A KR 880700454A KR 860700919 A KR860700919 A KR 860700919A KR 860700919 A KR860700919 A KR 860700919A KR 880700454 A KR880700454 A KR 880700454A
Authority
KR
South Korea
Prior art keywords
semiconductor
gas
group
bromine
field effect
Prior art date
Application number
KR860700919A
Other languages
English (en)
Other versions
KR920010128B1 (ko
Inventor
에드워드 이보트슨 데일
우칭 튜 찰스
Original Assignee
오레그 이.앨버
아메리칸 텔리폰 앤드 텔레그라프 캄파니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오레그 이.앨버, 아메리칸 텔리폰 앤드 텔레그라프 캄파니 filed Critical 오레그 이.앨버
Publication of KR880700454A publication Critical patent/KR880700454A/ko
Application granted granted Critical
Publication of KR920010128B1 publication Critical patent/KR920010128B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

내용 없음

Description

반도체 장치 및 그 제작 공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 선택적으로 도프된 헤테로 구조물 트랜지스터의 반도체 구조물의 측면도.

Claims (13)

  1. 선택적으로 도프된 헤테로 구조 또는 전계효과 트랜지스터를 제작하기에 특별히 유용하며, 부식성 가스에 의해 최소한 하나의 Ⅲ-V족 반도체 조성물이 에칭되는 최소한 하나의 8족 반도체 조성물을 구비하는 반도체 장치를 제작하기 위한 공정에 있어서, 부식성 가스는 0.0133과 13.33pa(0.1과 100millitorrs)사이의 압력에서 염소 가스 및 브롬가스로 부터 선택되는 최소한 하나의 가스를 구비하는 것을 특징으로 하는 반도체 장치 제작 공정.
  2. 제 1 항에 있어서, 부식성 가스 압력은 0.133과 1.33 pa(1과 10millitorrs)사이인 것을 특징으로 하는 반도체 장치 제작 공정.
  3. 제 1 항에 있어서, 표면온도는 60℃와 200℃ 사이에서, 에칭되며, 60℃와 140℃ 사이가 적절한 것을 특징으로 하는 반도체 장치 제작 공정.
  4. 제 3 항에 있어서, 온도 범위는 100과 110℃ 사이인 것을 특징으로 하는 반도체 장치 제작 공정.
  5. 제 1 항에 있어서, 하나 또는 그 이상의 제 2, 8족 반도체 조성물이 존재하는 곳에서, 제 1, 8족 반도체 조성물이 에칭될 때 마다 부식성 가스는 산화 가스를 포함하는 것을 특징으로 하는 반도체 장치 제작 공정.
  6. 제 5 항에 있어서, 산화물 가스는 산소 및 수증기로 부터 선택되는 것을 특징으로 하는 반도체 장치 제작 공정.
  7. 제 6 항에 있어서, 부식성 가스는 브롬이며 산화 가스는 수증기이며, 브롬 가스의 압력은 0.133 내지 1.33 pa(1 내지 10mTorrs)이며, 수증기의 압력은 0.0133 내지 0.67pa (0.1 내지 2mTorrs) 사이인 것을 특징으로 하는 반도체 장치 제작 공정.
  8. 제 7 항에 있어서, 제 1, 8 족 반도체 조성물은 갈륨 비화물이며 제 2, 8족 반도체 조성물은 최소한 10몰퍼센트 알루미늄을 가진 갈륨 알루미늄 질화물을 구비하는 것을 특징으로 하는 반도체 장치 제작 공정.
  9. 제 7 항에 있어서, 제 1, 8 족 반도체 조성물은 인듐 질화물이며, 제 2, 8 족 반도체 조성물은 알루미늄 인듐 질화물 또는 갈륨 인듐 질화물인 것을 특징으로 하는 반도체 장치 제작 공정.
  10. 제 1 항에 있어서, 부식성 가스는 필수적으로 브롬으로 구성되어 있는 것을 특징으로 하는 반도체 장치 제작 공정.
  11. 선행중 어느 한 항에 있어서, 상기 장치는 선택적으로 도프된 헤테로 구조물인 것을 특징으로 하는 반도체 장치 제작 공정.
  12. 제11항에 있어서, 상기 장치는 전계효과 트랜지스터인 것을 특징으로 하는 반도체 장치 제작 공정.
  13. 금속-반도체 전계 효과 트랜지스터 또는 변형된 도프 전계 효과 트랜지스터인 것을 특징으로 하는 제12항에 따른 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860700919A 1985-04-26 1986-03-27 반도체 장치 제작 공정 KR920010128B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US727669 1985-04-26
US06/727,669 US4689115A (en) 1985-04-26 1985-04-26 Gaseous etching process
US727,669 1985-04-26
PCT/US1986/000642 WO1986006546A1 (en) 1985-04-26 1986-03-27 Process for making semiconductor devices which involve gaseous etching

Publications (2)

Publication Number Publication Date
KR880700454A true KR880700454A (ko) 1988-03-15
KR920010128B1 KR920010128B1 (ko) 1992-11-16

Family

ID=24923542

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860700919A KR920010128B1 (ko) 1985-04-26 1986-03-27 반도체 장치 제작 공정

Country Status (7)

Country Link
US (1) US4689115A (ko)
EP (1) EP0221103B1 (ko)
JP (1) JPH07105382B2 (ko)
KR (1) KR920010128B1 (ko)
CA (1) CA1274154A (ko)
DE (1) DE3671811D1 (ko)
WO (1) WO1986006546A1 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192701A (en) * 1988-03-17 1993-03-09 Kabushiki Kaisha Toshiba Method of manufacturing field effect transistors having different threshold voltages
GB8905988D0 (en) * 1989-03-15 1989-04-26 Secr Defence Iii-v integrated circuits
JP2924239B2 (ja) * 1991-03-26 1999-07-26 三菱電機株式会社 電界効果トランジスタ
US5329137A (en) * 1991-07-17 1994-07-12 The United States Of America As Represented By The Secretary Of The Air Force Integrated total internal reflection optical switch utilizing charge storage in a quantum well
JPH06232099A (ja) 1992-09-10 1994-08-19 Mitsubishi Electric Corp 半導体装置の製造方法，半導体装置の製造装置，半導体レーザの製造方法，量子細線構造の製造方法，及び結晶成長方法
US5486235A (en) * 1993-08-09 1996-01-23 Applied Materials, Inc. Plasma dry cleaning of semiconductor processing chambers
KR100307986B1 (ko) * 1997-08-28 2002-05-09 가네꼬 히사시 반도체장치의제조방법
US7863197B2 (en) * 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
CN111106004A (zh) * 2018-10-29 2020-05-05 东泰高科装备科技有限公司 一种砷化镓刻蚀方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1041164B (de) * 1955-07-11 1958-10-16 Licentia Gmbh Verfahren zur Herstellung von elektrisch unsymmetrisch leitenden Systemen mit einem Halbleiterkristall
JPS539712B2 (ko) * 1972-05-18 1978-04-07
US4285763A (en) * 1980-01-29 1981-08-25 Bell Telephone Laboratories, Incorporated Reactive ion etching of III-V semiconductor compounds
US4397711A (en) * 1982-10-01 1983-08-09 Bell Telephone Laboratories, Incorporated Crystallographic etching of III-V semiconductor materials
US4498953A (en) * 1983-07-27 1985-02-12 At&T Bell Laboratories Etching techniques

Also Published As

Publication number Publication date
KR920010128B1 (ko) 1992-11-16
JPH07105382B2 (ja) 1995-11-13
EP0221103A1 (en) 1987-05-13
US4689115A (en) 1987-08-25
DE3671811D1 (de) 1990-07-12
WO1986006546A1 (en) 1986-11-06
EP0221103B1 (en) 1990-06-06
CA1274154A (en) 1990-09-18
JPS62502643A (ja) 1987-10-08

Similar Documents

Publication Publication Date Title
KR850005154A (ko) 화합물 반도체 집적회로 장치
KR850000775A (ko) 에칭기술
KR960030451A (ko) 확산마스크 및 그것을 이용한 pn접합소자의 제조방법
KR880700454A (ko) 반도체 장치 및 그 제작 공정
KR860000705A (ko) N-채널 및 p-채널 트랜지스터들을 포함하는 반도체 장치 및 그의 제조방법
KR870003571A (ko) 반도체 기억장치 및 그 제조방법
KR920015643A (ko) 전계효과트랜지스터
KR900019250A (ko) 화합물 반도체 장치
KR960002524A (ko) 3-5족 반도체 구조체 및 그 제조 방법
KR870002664A (ko) 집적회로내의 mos 전계효과 트랜지스터 제조방법
JPS55117281A (en) 3[5 group compound semiconductor hetero structure mosfet
KR920013776A (ko) 전계효과 트랜지스터
KR900001023A (ko) 트랜치 분리를 이용한 eprom 셀 및 이의 제조방법
JPS6423571A (en) Semiconductor element
KR910013568A (ko) 화합물 반도체 장치 및 그 제조방법
KR930017200A (ko) 접합전계효과 트랜지스터 및 그 제조방법
KR880009445A (ko) 반도체 장치의 제조방법
KR920015567A (ko) 반도체 메모리 셀 제조방법
KR920022385A (ko) 부가 산화막을 갖는 반도체 장치 및 그 제조 방법
KR980006069A (ko) 반도체 장치의 소자분리막 형성방법
KR920017188A (ko) 실리콘 습식 식각방법
Liao et al. An In 0.53 Ga 0.47 As p-channel MOSFET with plasma-grown native oxide insulated gate
KR940008097A (ko) 캐패시터 용량을 증대한 반도체 메모리 셀 제조방법
KR970018179A (ko) 반도체막의 식각방법
KR920018970A (ko) 박막 트랜지스터의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20011030

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee