KR930017200A - 접합전계효과 트랜지스터 및 그 제조방법 - Google Patents

접합전계효과 트랜지스터 및 그 제조방법 Download PDF

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KR930017200A
KR930017200A KR1019920000590A KR920000590A KR930017200A KR 930017200 A KR930017200 A KR 930017200A KR 1019920000590 A KR1019920000590 A KR 1019920000590A KR 920000590 A KR920000590 A KR 920000590A KR 930017200 A KR930017200 A KR 930017200A
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field effect
effect transistor
junction field
layer
semiconductor substrate
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KR1019920000590A
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정태화
김영순
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김광호
삼성전자 주식회사
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Priority to KR1019920000590A priority Critical patent/KR930017200A/ko
Priority to JP5002530A priority patent/JPH05275453A/ja
Priority to TW082100146A priority patent/TW234198B/zh
Priority to EP93300307A priority patent/EP0552067A2/en
Publication of KR930017200A publication Critical patent/KR930017200A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66924—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with an active layer made of a group 13/15 material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

JFET에 있어서 반도체기판의 결정면과 그 표면에 형성된 절연막의 형성방향에 의해 역경사면을 갖고 선택적으로 결정성장된 캡층들의 이격거리를 조절하여 게이트전극의 길이와 무관하게 유효채널길이를 조절할수 있으며, 또한, 상기 캡층들의 표면에 형성되어 채널로 이용되는 활성층을 보이드에 의해 반도체기판과 분리시킨다. 따라서, 캡층들의 역경사면들의 이격거리를 좁게하여 유효채널의 길이를 짧게 형성할수 있으며, 보이드에 의해 활성층과 반도체기판이 분리되어 누설전류에 의한 짧은 채널효과의 발생을 방지하고, 또한, 포토리소그래피 방법에 의한 게이트전극의 길이와 무관하게 에피택시에 의해 짧은 유효채널을 형성하므로 공정이 간단하다.

Description

접합전계효과 트랜지스터 및 그 조제방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 이 발명에 따른 접합전계효과 트랜지스터의 단면도, 제3(A) ~ (C)도는 이 발명에 따른 접합전계효과 트랜지스터의 제조공정도이다.

Claims (9)

  1. 접합전계효과 트랜지스터에 있어서, 소정의 결정면을 가지는 반절연성 반도체기판과, 상기 반도체기판의 표면에 주방향 플래트와 소정각을 가지며 길게 형성된 절연막과, 상기 절연막이 형성되지 않은 반도체기판의 표면에 역경사면들을 가지고 형성되며 표면이 소정거리 이격된 고농도의 제1도전형의 캡층들과, 상기 절연막 상부의 캡층들 표면에 형성되며 역경사면들이 합쳐져 표면이 평탄하게 형성된 제1도전층의 활성층과, 상기 절연막상부에 상기 활성층의 역경사면들에 의해 형성된 삼각형의 보이드와, 상기 게이트층과 상기 보이드양측의 캡층의 표면에 오믹접촉을 이루며 형성된 게이트전극과 소오스 및 드레이전극들을 구비한 접합전계효과 트랜지스터.
  2. 제1항에 있어서, 상기 반도체기판이 GaAs, InP 또는 GaP층 어느하나인 접합전계효과 트랜지스터.
  3. 제1항에 있어서, 상기 제1도전형이 N형이고, 제2도전형이 P형인 접합전계효과 트랜지스터.
  4. 제1항에 있어서, 상기 반도체기판의 결정면이 (100), (010) 또는 (001)중 어느하나인 접합전계효과 트랜지스터.
  5. 제1항에 있어서, 상기 절연막이 SiO2또는 Si3N4등의 절연막들중 어느 하나인 접합전계효과 트랜지스터.
  6. 제1항에 있어서, 상기 절연막이 주방향 플래트와 20 ~ 30°정도의 각도를 가지는 접합전계효과 트랜지스터.
  7. 접합전계효과 트랜지스터의 제조방법에 있어서, 소정의 결정면을 가지는 반절연성 반도체기판의 표면에 주방향 플래트와 소정각도를 이루는 줄무늬 형태의 절연막을 형성하는 제1공정과, 상기 절연막이 형성되어 있지 않은 반도체기판의 표면에 소정거리 이격된 역경사면들을 가지는 고농도 제1도전형의 캡층들을 형성하는 제2공정과, 상기 캡층의 표면에 제1도전형의 캡층들을 형성하는 제2공정과, 상기 캡층의 표면에 제1도전형의 활성층과 고농도 제2도전형의 게이트층을 형성하는 제3공정과, 상기 절연막 상부의 게이트층 표면에 게이트전극을 형성하고 나머지부분의 게이트층과 활성층을 제거하여 캡층들을 노출시키는 제4공정과, 상기 캡층들의 표면에 소오스 및 드레인 전극들을 형성하는 제5공정을 구비한 접합전계효과 트랜지스터의 제조방법.
  8. 제7항에 있어서, 상기 제2공정과 제3공정을 MOCVD 또는 MBE중 어느하나의 방법에 의해 한번의 스텝으로 형성하는 접합전계효과 트랜지스터의 제조방법.
  9. 제7항에 있어서, 상기 제4공정은 상기 게이트층의 표면에 오믹금속을 도포한 후 한번의 포토리소그래피에 의해 캡층들을 노출시키는 접합전계효과 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920000590A 1992-01-16 1992-01-16 접합전계효과 트랜지스터 및 그 제조방법 KR930017200A (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019920000590A KR930017200A (ko) 1992-01-16 1992-01-16 접합전계효과 트랜지스터 및 그 제조방법
JP5002530A JPH05275453A (ja) 1992-01-16 1993-01-11 接合ｆｅｔ及びその製造方法
TW082100146A TW234198B (ko) 1992-01-16 1993-01-12
EP93300307A EP0552067A2 (en) 1992-01-16 1993-01-18 Field effect transistor and a fabricating method thereof

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KR1019920000590A KR930017200A (ko) 1992-01-16 1992-01-16 접합전계효과 트랜지스터 및 그 제조방법

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KR930017200A true KR930017200A (ko) 1993-08-30

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JP (1) JPH05275453A (ko)
KR (1) KR930017200A (ko)
TW (1) TW234198B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100351888B1 (ko) * 1997-12-31 2002-11-18 주식회사 하이닉스반도체 반도체소자의 배선구조 및 형성방법

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2412009B (en) * 2004-03-11 2006-01-25 Toshiba Research Europ Limited A semiconductor device and method of its manufacture
US8779554B2 (en) * 2012-03-30 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. MOSFETs with channels on nothing and methods for forming the same
WO2022230293A1 (ja) * 2021-04-30 2022-11-03 ソニーセミコンダクタソリューションズ株式会社 半導体装置

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Publication number Priority date Publication date Assignee Title
US4295267A (en) * 1980-07-18 1981-10-20 Trw Inc. Two-mask VJ-FET transistor structure
US4499481A (en) * 1983-09-14 1985-02-12 The United States Of America As Represented By The Secretary Of The Navy Heterojunction Schottky gate MESFET with lower channel ridge barrier
JPS61260679A (ja) * 1985-05-15 1986-11-18 Fujitsu Ltd 電界効果トランジスタ
FR2631744A1 (fr) * 1988-04-29 1989-11-24 Thomson Csf Transistor a effet de champ, son procede de realisation, et procede d'integration monolithique d'un transistor a effet de champ et d'un laser

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100351888B1 (ko) * 1997-12-31 2002-11-18 주식회사 하이닉스반도체 반도체소자의 배선구조 및 형성방법

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EP0552067A2 (en) 1993-07-21
TW234198B (ko) 1994-11-11
EP0552067A3 (ko) 1994-12-21

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