KR880001044A - 반도체 장치 제조방법 - Google Patents
반도체 장치 제조방법 Download PDFInfo
- Publication number
- KR880001044A KR880001044A KR870005948A KR870005948A KR880001044A KR 880001044 A KR880001044 A KR 880001044A KR 870005948 A KR870005948 A KR 870005948A KR 870005948 A KR870005948 A KR 870005948A KR 880001044 A KR880001044 A KR 880001044A
- Authority
- KR
- South Korea
- Prior art keywords
- laser beam
- wiring
- aluminum film
- aluminum
- semiconductor device
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
- H01L23/5254—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/093—Laser beam treatment in general
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예에 의해서 반도체 장치를 제조하는 방법을 도시한 단면도. 제2도는 반도체장치를 제조하는 종래의 방법을 도시한 단면도. 제3도는 본 발명의 실시예로 달성된 효과를 설명하는 실험데이타도.
Claims (6)
- 알미늄막으로 이루어지는 제1배선상에 형성된 절연체 막내에 콘택트홀을 형성시키는 단계와, 제2배선을 위한 알미늄막으로 절연체막을 덮는 단계와, 제2배선을 위하여 알미늄막상에 위로부터 레이저광선 펄스들을 조사하는 단계와, 알미늄막을 패턴닝시켜 제2배선을 형성시키는 단계를 포함하는 반도체 장치 제조방법.
- 제1항에 있어서, 알미늄막들은 각각이 알미늄의 막이나 주성분이 알미늄으로 된 알미늄 합금인 것을 특징으로 하는 반도체 장치 제조방법.
- 제1항에 있어서, 레이저 광선들은 에너지 강도 5 - 12J/㎠로 인가되는 것을 특징으로 하는 반도체 장치 제조방법.
- 제1항에 있어서, 엑시미어 레이저 광선이 ArF 엑시미어 레이저 광선, KrF2엑시미어 레이저광선, XeCl엑시미어 레이저 광선과 TEA-CO2레이저 광선으로부터 선택되는 것을 특징으로 하는 반도체 장치 제조방법.
- 제1항에 있어서, 제1배선을 위한 알미늄막상에 형성된 산화물이나 흡수물이 레이저 광선펄스를 인가함으로써 제거되는 것을 특직으로하는 반도체장치 제조방법.
- 제1항에 있어서, 제2배선을 위한 알미늄막이 순간적으로 용융되어 콘택트홀내로 부분적으로 흘러들어 가는 것을 특징으로 하는 반도체 장치 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61-137509 | 1986-06-13 | ||
JP61137509A JPS62293740A (ja) | 1986-06-13 | 1986-06-13 | 半導体装置の製造方法 |
JP137509 | 1986-06-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880001044A true KR880001044A (ko) | 1988-03-31 |
KR900004268B1 KR900004268B1 (ko) | 1990-06-18 |
Family
ID=15200330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019870005948A KR900004268B1 (ko) | 1986-06-13 | 1987-06-12 | 반도체 장치 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4800179A (ko) |
EP (1) | EP0251523B1 (ko) |
JP (1) | JPS62293740A (ko) |
KR (1) | KR900004268B1 (ko) |
DE (1) | DE3766890D1 (ko) |
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US4657778A (en) * | 1984-08-01 | 1987-04-14 | Moran Peter L | Multilayer systems and their method of production |
US4681795A (en) * | 1985-06-24 | 1987-07-21 | The United States Of America As Represented By The Department Of Energy | Planarization of metal films for multilevel interconnects |
US4674176A (en) * | 1985-06-24 | 1987-06-23 | The United States Of America As Represented By The United States Department Of Energy | Planarization of metal films for multilevel interconnects by pulsed laser heating |
-
1986
- 1986-06-13 JP JP61137509A patent/JPS62293740A/ja active Pending
-
1987
- 1987-06-09 DE DE8787305084T patent/DE3766890D1/de not_active Expired - Fee Related
- 1987-06-09 EP EP87305084A patent/EP0251523B1/en not_active Expired - Lifetime
- 1987-06-12 KR KR1019870005948A patent/KR900004268B1/ko not_active IP Right Cessation
- 1987-06-12 US US07/060,923 patent/US4800179A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPS62293740A (ja) | 1987-12-21 |
DE3766890D1 (de) | 1991-02-07 |
EP0251523A1 (en) | 1988-01-07 |
EP0251523B1 (en) | 1991-01-02 |
US4800179A (en) | 1989-01-24 |
KR900004268B1 (ko) | 1990-06-18 |
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