KR860007736A - 반도체 장치와 그 제조 방법 및 그 제조방법을 사용하는 리이드 프레임 - Google Patents
반도체 장치와 그 제조 방법 및 그 제조방법을 사용하는 리이드 프레임 Download PDFInfo
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- KR860007736A KR860007736A KR1019860001027A KR860001027A KR860007736A KR 860007736 A KR860007736 A KR 860007736A KR 1019860001027 A KR1019860001027 A KR 1019860001027A KR 860001027 A KR860001027 A KR 860001027A KR 860007736 A KR860007736 A KR 860007736A
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 실시예 1인 반도체 장치의 일부를 도시한 단면도.
제2도 A는, 실시예 1의 반도체 장치의 제조에 이용되는 리이드 프레임의 단위를 도시한 평면도.
제2도 B는, 제2도 A에 있어서의 ⅡB-ⅡB 사시단면도.
제3도는, 본 발명에 의한 실시예 2인 반도체 장치의 일부를 도시한 단면도.
Claims (14)
- 외부 리이드가 아랫쪽으로 접어꾸부러져서 된 수지봉지형 반도체 장치로서, 팩케이지측끝 근방의 리이드 절곡부에 그 리이드의 바깥쪽면 또는 안쪽면의 적어도 한쪽에 놋치를 마련하여 된 반도체 장치.
- 바깥쪽 면의 놋치가 곡율반경이 최대인 리이드 절곡부에 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
- 안쪽면의 놋치가 곡율반경이 최대의 리이드 절곡부를 피하여서 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
- 리이드의 길이 방향에 있어서의 놋치의 단면 형상이 V자형, 구형 또는 대략 반원형인 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
- 리이드가 동계통의 재료 또는 철계통의 재료로 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
- 반도체 장치는 프라스틱 리이 데드 칩 캐리어형 반도체 장치인 것을 특징으로 하는 특허청구의 범위 제1항 기재의 반도체 장치.
- 피렛 취부 공정, 와이어 본딩 공정, 몰드 공정, 리이드 절단 공정 및 리이드 절곡 공정으로 된 리이드 프레임을 사용하는 반도체 장치의 제조 방법으로서, 상기의 어느 공정전에, 몰드 형성되는 팩케이지측 끝근방 또는 이에 상당하는 위치의 외부 리이드부에 대해서, 절곡 방향과 반대쪽의 그 리이드의 바깥쪽면 또는 절곡방향인 안쪽면의 적어도 한쪽에 놋치를 마련하는 반도체 장치의 제조 방법.
- 안쪽면에 형성되어 있는 놋치가, 바깥쪽 면의 그것보다 바깥쪽에 마련되어 있는 것을 특징으로 하는 특허청구의 범위 제7항 기재의 반도체 장치의 제조 방법.
- 리이드의 길이방향에 있어서의 놋치의 단면 형상이 V자형, 구형 또는 대략 반원형인 것을 특징으로 하는 특허청구의 범위 제7항 기재의 반도체 장치의 제조 방법.
- 리이드 프레임이 동계통 또는 철계통재료로 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제7항 기재의 반도체 장치의 제조 방법.
- 수지봉지형 반도체장치의 제조에 이용되는 리이드 프레임으로서, 타이바 연결부 또는 그 근방의 외부 리이드부의 윗면 또는 아랫면의 적어도 한쪽에 놋치가 마련되어서 되는 리이드 프레임.
- 아랫면에 형성되어 있는 놋치가, 윗면의 그것보다 바깥쪽에 마련되어 있는 것을 특징으로 하는 특허청구의 범위 제11항 기재의 리이드 프레임.
- 리이드의 길이 방향에 있어서의 놋치의 단면 형상이, V자형 구형 또는 대략 반원형인 것을 특징으로 하는 특허청구의 범위 제11항 기재의 리이드 프레임.
- 리이드 프레임이 동계통 또는 철계통 재료로 형성되어 있는 것을 특징으로 하는 특허청구의 범위 제11항 리이드 프레임.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60058361A JPS61218150A (ja) | 1985-03-25 | 1985-03-25 | 半導体装置、それに用いるリ−ドフレ−ムおよびその製造方法 |
JP58361 | 1985-03-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR860007736A true KR860007736A (ko) | 1986-10-17 |
Family
ID=13082175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860001027A KR860007736A (ko) | 1985-03-25 | 1986-02-14 | 반도체 장치와 그 제조 방법 및 그 제조방법을 사용하는 리이드 프레임 |
Country Status (2)
Country | Link |
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JP (1) | JPS61218150A (ko) |
KR (1) | KR860007736A (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2507053B2 (ja) * | 1989-06-14 | 1996-06-12 | 松下電子工業株式会社 | Jリ―ドパッケ―ジ型半導体装置 |
JP2008205329A (ja) * | 2007-02-22 | 2008-09-04 | Nichia Chem Ind Ltd | 半導体装置 |
JP5268468B2 (ja) * | 2008-07-22 | 2013-08-21 | シャープ株式会社 | 表面実装型赤外線受光ユニット、表面実装型赤外線受光ユニット製造方法、および電子機器 |
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1985
- 1985-03-25 JP JP60058361A patent/JPS61218150A/ja active Pending
-
1986
- 1986-02-14 KR KR1019860001027A patent/KR860007736A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
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JPS61218150A (ja) | 1986-09-27 |
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