KR860004461A - 보장된 횡단면을 갖는 배선으로 된 반도체 메모리장치 - Google Patents

보장된 횡단면을 갖는 배선으로 된 반도체 메모리장치

Info

Publication number
KR860004461A
KR860004461A KR1019850008822A KR850008822A KR860004461A KR 860004461 A KR860004461 A KR 860004461A KR 1019850008822 A KR1019850008822 A KR 1019850008822A KR 850008822 A KR850008822 A KR 850008822A KR 860004461 A KR860004461 A KR 860004461A
Authority
KR
South Korea
Prior art keywords
wiring
section
memory device
semiconductor memory
guaranteed cross
Prior art date
Application number
KR1019850008822A
Other languages
English (en)
Other versions
KR900000634B1 (ko
Inventor
타이지 에마
다까시 야부
Original Assignee
후지쓰가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰가부시끼가이샤 filed Critical 후지쓰가부시끼가이샤
Publication of KR860004461A publication Critical patent/KR860004461A/ko
Application granted granted Critical
Publication of KR900000634B1 publication Critical patent/KR900000634B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019850008822A 1984-11-26 1985-11-26 보장된 횡단면을 갖는 배선으로 된 반도체 메모리장치 KR900000634B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59-248946 1984-11-26
JP59248946A JPS61127161A (ja) 1984-11-26 1984-11-26 半導体記憶装置

Publications (2)

Publication Number Publication Date
KR860004461A true KR860004461A (ko) 1986-06-23
KR900000634B1 KR900000634B1 (ko) 1990-02-01

Family

ID=17185768

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850008822A KR900000634B1 (ko) 1984-11-26 1985-11-26 보장된 횡단면을 갖는 배선으로 된 반도체 메모리장치

Country Status (5)

Country Link
US (1) US4807017A (ko)
EP (1) EP0183517B1 (ko)
JP (1) JPS61127161A (ko)
KR (1) KR900000634B1 (ko)
DE (1) DE3569067D1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0787219B2 (ja) * 1986-09-09 1995-09-20 三菱電機株式会社 半導体記憶装置
JPH07120755B2 (ja) * 1986-10-24 1995-12-20 日本電気株式会社 半導体記憶装置
DE3807162A1 (de) * 1987-07-02 1989-01-12 Mitsubishi Electric Corp Halbleiterspeichereinrichtung
JP2712079B2 (ja) * 1988-02-15 1998-02-10 株式会社東芝 半導体装置
JPH0263163A (ja) * 1988-08-29 1990-03-02 Nec Corp 不揮発性半導体記憶装置
FR2638285B1 (fr) * 1988-10-25 1992-06-19 Commissariat Energie Atomique Circuit integre a haute densite d'integration tel que memoire eprom et procede d'obtention correspondant
JP2503661B2 (ja) * 1989-06-28 1996-06-05 日本電気株式会社 半導体メモリ素子およびその製造方法
JPH03109767A (ja) * 1989-09-25 1991-05-09 Nec Corp 半導体集積回路装置
US5170243A (en) * 1991-11-04 1992-12-08 International Business Machines Corporation Bit line configuration for semiconductor memory
JPH09252058A (ja) * 1996-03-15 1997-09-22 Rohm Co Ltd 半導体記憶装置の製造方法および半導体記憶装置
US5751038A (en) * 1996-11-26 1998-05-12 Philips Electronics North America Corporation Electrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layers
US5877976A (en) * 1997-10-28 1999-03-02 International Business Machines Corporation Memory system having a vertical bitline topology and method therefor
DE10155023B4 (de) * 2001-11-05 2008-11-06 Qimonda Ag Leitungsanordnung für Bitleitungen zur Kontaktierung mindestens einer Speicherzelle und Verfahren zur Herstellung einer Leitungsanordnung für Bitleitungen

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001871A (en) * 1968-06-17 1977-01-04 Nippon Electric Company, Ltd. Semiconductor device
US3946421A (en) * 1974-06-28 1976-03-23 Texas Instruments Incorporated Multi phase double level metal charge coupled device
DE2720533A1 (de) * 1977-05-06 1978-11-09 Siemens Ag Monolithisch integrierte schaltungsanordnung mit ein-transistor- speicherelementen
DE2743619A1 (de) * 1977-09-28 1979-03-29 Siemens Ag Halbleiter-speicherelement und verfahren zu seiner herstellung
US4328563A (en) * 1979-01-12 1982-05-04 Mostek Corporation High density read only memory
EP0154685B1 (en) * 1980-01-25 1990-04-18 Kabushiki Kaisha Toshiba Semiconductor memory device
US4536941A (en) * 1980-03-21 1985-08-27 Kuo Chang Kiang Method of making high density dynamic memory cell
JPS602784B2 (ja) * 1982-12-20 1985-01-23 富士通株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPS61127161A (ja) 1986-06-14
US4807017A (en) 1989-02-21
DE3569067D1 (en) 1989-04-27
KR900000634B1 (ko) 1990-02-01
EP0183517B1 (en) 1989-03-22
EP0183517A3 (en) 1986-12-30
EP0183517A2 (en) 1986-06-04

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Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee