KR860007747A - 다이내믹형 반도체기억장치 - Google Patents

다이내믹형 반도체기억장치

Info

Publication number
KR860007747A
KR860007747A KR1019860002358A KR860002358A KR860007747A KR 860007747 A KR860007747 A KR 860007747A KR 1019860002358 A KR1019860002358 A KR 1019860002358A KR 860002358 A KR860002358 A KR 860002358A KR 860007747 A KR860007747 A KR 860007747A
Authority
KR
South Korea
Prior art keywords
memory device
type semiconductor
semiconductor memory
dynamic type
dynamic
Prior art date
Application number
KR1019860002358A
Other languages
English (en)
Other versions
KR900001226B1 (ko
Inventor
도오루 후루야마
시게요시 와타나베
다쯔오 이까와
Original Assignee
가부시끼가이샤 도오시바
도오시바 마이크로-컴퓨터 엔지니어링 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60066757A external-priority patent/JPS61227292A/ja
Priority claimed from JP60194695A external-priority patent/JPS6254461A/ja
Application filed by 가부시끼가이샤 도오시바, 도오시바 마이크로-컴퓨터 엔지니어링 가부시끼가이샤 filed Critical 가부시끼가이샤 도오시바
Publication of KR860007747A publication Critical patent/KR860007747A/ko
Application granted granted Critical
Publication of KR900001226B1 publication Critical patent/KR900001226B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
KR1019860002358A 1985-03-30 1986-03-28 다이내믹형 반도체기억장치 KR900001226B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP60066757A JPS61227292A (ja) 1985-03-30 1985-03-30 ダイナミツク型半導体メモリ
JP60-66757 1985-03-30
JP60194695A JPS6254461A (ja) 1985-09-03 1985-09-03 半導体記憶装置
JP60-194695 1985-09-03

Publications (2)

Publication Number Publication Date
KR860007747A true KR860007747A (ko) 1986-10-17
KR900001226B1 KR900001226B1 (ko) 1990-03-05

Family

ID=26407957

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860002358A KR900001226B1 (ko) 1985-03-30 1986-03-28 다이내믹형 반도체기억장치

Country Status (2)

Country Link
US (1) US4733374A (ko)
KR (1) KR900001226B1 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980860A (en) * 1986-06-27 1990-12-25 Texas Instruments Incorporated Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry
US5214601A (en) * 1986-12-11 1993-05-25 Mitsubishi Denki Kabushiki Kaisha Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers
JPS63183691A (ja) * 1987-01-26 1988-07-29 Mitsubishi Electric Corp 半導体記憶装置
JPS63239674A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd ダイナミツク型ｒａｍ
JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
KR930001737B1 (ko) * 1989-12-29 1993-03-12 삼성전자 주식회사 반도체 메모리 어레이의 워드라인 배열방법
KR920010344B1 (ko) * 1989-12-29 1992-11-27 삼성전자주식회사 반도체 메모리 어레이의 구성방법
US5214600A (en) * 1989-12-30 1993-05-25 Samsung Electronics Co., Ltd. Semiconductor memory array having interdigitated bit-line structure
KR920005150A (ko) * 1990-08-31 1992-03-28 김광호 씨모오스디램의 센스 앰프 구성방법
FR2668640A1 (fr) * 1990-10-30 1992-04-30 Samsung Electronics Co Ltd Memoire a semi-conducteurs possedant des lignes de bit et des lignes de mot qui se croisent.
DE4034693A1 (de) * 1990-10-31 1992-05-07 Samsung Electronics Co Ltd Halbleiterspeichervorrichtung
US5276641A (en) * 1991-12-12 1994-01-04 International Business Machines Corporation Hybrid open folded sense amplifier architecture for a memory device
US5303196A (en) * 1992-05-22 1994-04-12 International Business Machines Corporation Open bit line memory devices and operational method
JP3086757B2 (ja) * 1992-09-28 2000-09-11 三菱電機株式会社 スタティックランダムアクセスメモリ
JP2004247436A (ja) 2003-02-12 2004-09-02 Sharp Corp 半導体記憶装置、表示装置及び携帯電子機器
US8411479B2 (en) * 2009-07-23 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits, systems, and methods for routing the memory circuits
JP6070526B2 (ja) * 2013-12-11 2017-02-01 豊田合成株式会社 半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells
US4045783A (en) * 1976-04-12 1977-08-30 Standard Microsystems Corporation Mos one transistor cell ram having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry
JPS57111061A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Semiconductor memory unit

Also Published As

Publication number Publication date
US4733374A (en) 1988-03-22
KR900001226B1 (ko) 1990-03-05

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