KR900012276A - 다이내믹형 반도체기억장치 - Google Patents
다이내믹형 반도체기억장치Info
- Publication number
- KR900012276A KR900012276A KR1019900000195A KR900000195A KR900012276A KR 900012276 A KR900012276 A KR 900012276A KR 1019900000195 A KR1019900000195 A KR 1019900000195A KR 900000195 A KR900000195 A KR 900000195A KR 900012276 A KR900012276 A KR 900012276A
- Authority
- KR
- South Korea
- Prior art keywords
- memory device
- type semiconductor
- semiconductor memory
- dynamic type
- dynamic
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Dram (AREA)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP89-2452 | 1988-01-09 | ||
JP89-2453 | 1988-01-09 | ||
JP89-2454 | 1988-01-09 | ||
JP1002454A JPH02183491A (ja) | 1989-01-09 | 1989-01-09 | 半導体装置およびダイナミック型半導体記憶装置 |
JP1002453A JP2845467B2 (ja) | 1989-01-09 | 1989-01-09 | ダイナミック型半導体記憶装置 |
JP01002452A JP3083094B2 (ja) | 1989-01-09 | 1989-01-09 | ダイナミック型半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900012276A true KR900012276A (ko) | 1990-08-03 |
KR940009285B1 KR940009285B1 (ko) | 1994-10-06 |
Family
ID=27275352
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900000195A KR940009285B1 (ko) | 1988-01-09 | 1990-01-09 | 다이내믹형 반도체기억장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5144583A (ko) |
KR (1) | KR940009285B1 (ko) |
DE (1) | DE4000429C2 (ko) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2953708B2 (ja) * | 1989-07-31 | 1999-09-27 | 株式会社東芝 | ダイナミック型半導体記憶装置 |
JPH03171662A (ja) * | 1989-11-29 | 1991-07-25 | Sharp Corp | 信号線システム |
US5287322A (en) * | 1991-07-17 | 1994-02-15 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit dual-port memory device having reduced capacitance |
US5311477A (en) * | 1991-07-17 | 1994-05-10 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit memory device having flash clear |
JP3440335B2 (ja) * | 1993-08-18 | 2003-08-25 | 日本テキサス・インスツルメンツ株式会社 | 半導体メモリ装置 |
KR100215595B1 (ko) * | 1993-09-21 | 1999-08-16 | 니시무로 타이죠 | 다이나믹형 반도체 기억장치 |
US5440516A (en) * | 1994-01-27 | 1995-08-08 | Sgs-Thomson Microelectronics, Inc. | Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same |
EP0697735B1 (en) * | 1994-08-15 | 2002-03-27 | International Business Machines Corporation | Single twist layout and method for paired line conductors of integrated circuits |
US5907508A (en) * | 1997-10-28 | 1999-05-25 | International Business Machines Corporation | Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell |
US5877976A (en) * | 1997-10-28 | 1999-03-02 | International Business Machines Corporation | Memory system having a vertical bitline topology and method therefor |
US5956286A (en) * | 1997-10-28 | 1999-09-21 | International Business Machines Corporation | Data processing system and method for implementing a multi-port memory cell |
US5870349A (en) * | 1997-10-28 | 1999-02-09 | International Business Machines Corporation | Data processing system and method for generating memory control signals with clock skew tolerance |
KR100278656B1 (ko) * | 1998-05-12 | 2001-02-01 | 윤종용 | 트위스트된비트라인구조를갖는반도체메모리장치 |
KR100300047B1 (ko) * | 1998-05-30 | 2001-09-22 | 김영환 | 노이즈 간섭 방지를 위한 데이터라인 배열 구조를 갖는 반도체 메모리 소자 |
DE19908428C2 (de) * | 1999-02-26 | 2000-12-07 | Siemens Ag | Halbleiterspeicheranordnung mit Bitleitungs-Twist |
US6124199A (en) * | 1999-04-28 | 2000-09-26 | International Business Machines Corporation | Method for simultaneously forming a storage-capacitor electrode and interconnect |
US6201272B1 (en) | 1999-04-28 | 2001-03-13 | International Business Machines Corporation | Method for simultaneously forming a storage-capacitor electrode and interconnect |
US6320780B1 (en) * | 1999-09-28 | 2001-11-20 | Infineon Technologies North America Corp. | Reduced impact from coupling noise in diagonal bitline architectures |
US6327170B1 (en) * | 1999-09-28 | 2001-12-04 | Infineon Technologies Ag | Reducing impact of coupling noise in multi-level bitline architecture |
US6188598B1 (en) * | 1999-09-28 | 2001-02-13 | Infineon Technologies North America Corp. | Reducing impact of coupling noise |
US6504246B2 (en) * | 1999-10-12 | 2003-01-07 | Motorola, Inc. | Integrated circuit having a balanced twist for differential signal lines |
US6498758B1 (en) * | 2002-01-16 | 2002-12-24 | Lsi Logic Corporation | Twisted bitlines to reduce coupling effects (dual port memories) |
JP3984090B2 (ja) * | 2002-04-01 | 2007-09-26 | 株式会社東芝 | 強誘電体メモリ装置 |
US6909663B1 (en) | 2003-09-26 | 2005-06-21 | Lattice Semiconductor Corporation | Multiport memory with twisted bitlines |
US6992939B2 (en) * | 2004-01-26 | 2006-01-31 | Micron Technology, Inc. | Method and apparatus for identifying short circuits in an integrated circuit device |
US20100044093A1 (en) * | 2008-08-25 | 2010-02-25 | Wilinx Corporation | Layout geometries for differential signals |
TWI520273B (zh) * | 2011-02-02 | 2016-02-01 | 半導體能源研究所股份有限公司 | 半導體儲存裝置 |
US8780614B2 (en) * | 2011-02-02 | 2014-07-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device |
US10861787B1 (en) * | 2019-08-07 | 2020-12-08 | Micron Technology, Inc. | Memory device with bitline noise suppressing scheme |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2919166C2 (de) * | 1978-05-12 | 1986-01-02 | Nippon Electric Co., Ltd., Tokio/Tokyo | Speichervorrichtung |
JPS60254489A (ja) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | 半導体記憶装置 |
JPS6251096A (ja) * | 1985-08-28 | 1987-03-05 | Nec Corp | 半導体記憶装置 |
EP0293578B1 (en) * | 1987-06-05 | 1993-09-01 | International Business Machines Corporation | High density layout for memory arrays |
-
1990
- 1990-01-04 US US07/461,121 patent/US5144583A/en not_active Expired - Lifetime
- 1990-01-09 KR KR1019900000195A patent/KR940009285B1/ko not_active IP Right Cessation
- 1990-01-09 DE DE4000429A patent/DE4000429C2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE4000429A1 (de) | 1990-07-12 |
US5144583A (en) | 1992-09-01 |
KR940009285B1 (ko) | 1994-10-06 |
DE4000429C2 (de) | 1994-12-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20090928 Year of fee payment: 16 |
|
EXPY | Expiration of term |