KR850007156A - 다이나믹형 랜덤억세스 메모리 - Google Patents

다이나믹형 랜덤억세스 메모리 Download PDF

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Publication number
KR850007156A
KR850007156A KR1019850001421A KR850001421A KR850007156A KR 850007156 A KR850007156 A KR 850007156A KR 1019850001421 A KR1019850001421 A KR 1019850001421A KR 850001421 A KR850001421 A KR 850001421A KR 850007156 A KR850007156 A KR 850007156A
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KR
South Korea
Prior art keywords
terminal
voltage level
memory cell
inductive
random access
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KR1019850001421A
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English (en)
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KR910000383B1 (ko
Inventor
유끼마사 우찌다
Original Assignee
사바 쇼오이찌
가부시끼가이샤 도오시바
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Publication of KR850007156A publication Critical patent/KR850007156A/ko
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Publication of KR910000383B1 publication Critical patent/KR910000383B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Abstract

내용 없음

Description

다이나믹형 랜덤억세스 메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명의 구체적인 실시예에 따른 DRAM의 회로도. 제9도는 제6도에 나타난 DRAM에서 사용되는 전압공급회로의 회로도. 제10도는 제6도 DRAM의 각 부분동작을 표시하는 파형을 설명하기 위한 타이밍챠트.
101 : 전압공급단자, 102 : 드레인단자, 103 : 소오스단자, 104 : 게이트단자, 111,112,113,114 : 메모리셀, 121, 122, 221, 222 : 더미셀, 131, 231 : 감지증폭기, 132, 232 : 선충전회로, 141 : 게이트산화막, 142 : 필드산화막, 211,212,213,214 : 메모리셀, 241 : 전압공급회로, 21 : Vcc전원 공급선, 22 : Vss전원 공급선, 23 : 출력전압선, C,C´: 캐퍼시터, Tt : MOS트랜지스터,: 비트선, Ｗ1,Ｗ2: 워드선, DＷ1,DW : 더미워드선, SL : 감지랫치신호, TSL,TPG1∼TPG8, Td,T1,T2: 트랜지스터, PG : 선충전신호, D,D1,D2: 다이오드소자, TP: P채널 트랜지스터, TN: N채널 트랜지스터, I1,I2: CMOS인버터.

Claims (1)

  1. 공급전압단자, 상기 공급전압단자와 제2충전단자가 연결된 제1충전단자를 갖는 용량성수단, 상기 제2충전단자와 제2유도단자가 연결된 제1유도단자를 갖고 상기 제1, 제2 유도단자 사이에 유도통로를 형성시키며 상기 유도통로의 임피던스를 제어하기 위한 제어단자를 갖는 스위치수단등을 포함하는 메모리셀; 상기 메모리셀이 다른 전압레벨로 선택될때나 비선택될때 어떤 전압레벨을 갖는 제어단자가 연결된 워드선; 상기 제2유도단자가 연결되는 비트선등을 구성하는 다이나믹형 랜덤억세스메모리에 있어서, 상기 메모리셀이 선택되지 않을때 상기 워드선의 다른 전압레벨과 상기 제1유도단자의 전압레벨사이에 전압레벨을 상기 비트선에 적용시키기 위한 수단, 거기에다 상기 메모리셀이 선택되지 않을때 유도통로를 통해 흐르는 리이크 전류를 방지하기 위한 수단등을 구성함을 특징으로 하는 다이나믹형 랜덤억세스메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850001421A 1984-03-09 1985-03-06 다이나믹형 랜덤억세스메모리 KR910000383B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP59-45202 1984-03-09
JP59045202A JPS60191499A (ja) 1984-03-09 1984-03-09 ダイナミツク型ランダムアクセスメモリ
JP45202 1989-02-28

Publications (2)

Publication Number Publication Date
KR850007156A true KR850007156A (ko) 1985-10-30
KR910000383B1 KR910000383B1 (ko) 1991-01-24

Family

ID=12712677

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850001421A KR910000383B1 (ko) 1984-03-09 1985-03-06 다이나믹형 랜덤억세스메모리

Country Status (5)

Country Link
US (1) US4794571A (ko)
EP (1) EP0154547B1 (ko)
JP (1) JPS60191499A (ko)
KR (1) KR910000383B1 (ko)
DE (1) DE3586064D1 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
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US4679172A (en) * 1985-05-28 1987-07-07 American Telephone And Telegraph Company, At&T Bell Laboratories Dynamic memory with increased data retention time
JPH0770216B2 (ja) * 1985-11-22 1995-07-31 株式会社日立製作所 半導体集積回路
JPS63117391A (ja) * 1986-11-04 1988-05-21 Mitsubishi Electric Corp 半導体記憶装置
JPS63121197A (ja) * 1986-11-07 1988-05-25 Fujitsu Ltd 半導体記憶装置
US5007022A (en) * 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
JPH01166399A (ja) * 1987-12-23 1989-06-30 Toshiba Corp スタティック型ランダムアクセスメモリ
JPH01171194A (ja) * 1987-12-25 1989-07-06 Nec Ic Microcomput Syst Ltd 半導体記憶装置
US5153701A (en) * 1987-12-28 1992-10-06 At&T Bell Laboratories Semiconductor device with low defect density oxide
USRE40132E1 (en) 1988-06-17 2008-03-04 Elpida Memory, Inc. Large scale integrated circuit with sense amplifier circuits for low voltage operation
KR0137768B1 (ko) * 1988-11-23 1998-06-01 존 지. 웨브 단일 트랜지스터 메모리 셀과 함께 사용하는 고속 자동 센스 증폭기
GB9007793D0 (en) * 1990-04-06 1990-06-06 Foss Richard C Dram cell plate and precharge voltage generator
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
JP3068377B2 (ja) * 1993-06-30 2000-07-24 日本電気株式会社 ダイナミック形半導体記憶装置
EP0663666B1 (de) * 1994-01-12 1999-03-03 Siemens Aktiengesellschaft Integrierte Halbleiterspeicherschaltung und Verfahren zu ihrem Betrieb
FR2787922B1 (fr) * 1998-12-23 2002-06-28 St Microelectronics Sa Cellule memoire a programmation unique en technologie cmos
JP4084149B2 (ja) * 2002-09-13 2008-04-30 富士通株式会社 半導体記憶装置

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US3514765A (en) * 1969-05-23 1970-05-26 Shell Oil Co Sense amplifier comprising cross coupled mosfet's operating in a race mode for single device per bit mosfet memories
US3678473A (en) * 1970-06-04 1972-07-18 Shell Oil Co Read-write circuit for capacitive memory arrays
BE789500A (fr) * 1971-09-30 1973-03-29 Siemens Ag Memoire a semiconducteurs avec elements de memorisation a un seul transistor
DE2454988C2 (de) * 1974-11-20 1976-09-09 Siemens Ag Schaltungsanordnung zur verhinderung des verlustes der in den kapazitaeten von nach dem dynamischen prinzip aufgebauten speicherzellen eines mos- speichers gespeicherten informationen
US4099265A (en) * 1976-12-22 1978-07-04 Motorola, Inc. Sense line balance circuit for static random access memory
JPS5399736A (en) * 1977-02-10 1978-08-31 Toshiba Corp Semiconductor memory unit
JPS5457921A (en) * 1977-10-18 1979-05-10 Fujitsu Ltd Sense amplifier circuit
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JPS5661085A (en) * 1979-10-23 1981-05-26 Toshiba Corp Semiconductor memory device
JPS5712483A (en) * 1980-06-23 1982-01-22 Nec Corp Transistor circuit

Also Published As

Publication number Publication date
EP0154547B1 (en) 1992-05-20
KR910000383B1 (ko) 1991-01-24
EP0154547A3 (en) 1987-01-21
JPH0587914B2 (ko) 1993-12-20
US4794571A (en) 1988-12-27
DE3586064D1 (de) 1992-06-25
EP0154547A2 (en) 1985-09-11
JPS60191499A (ja) 1985-09-28

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