KR20210102252A - 직접 피드포워드 회로를 갖는 위상 고정 루프(pll) - Google Patents

직접 피드포워드 회로를 갖는 위상 고정 루프(pll) Download PDF

Info

Publication number
KR20210102252A
KR20210102252A KR1020217017759A KR20217017759A KR20210102252A KR 20210102252 A KR20210102252 A KR 20210102252A KR 1020217017759 A KR1020217017759 A KR 1020217017759A KR 20217017759 A KR20217017759 A KR 20217017759A KR 20210102252 A KR20210102252 A KR 20210102252A
Authority
KR
South Korea
Prior art keywords
node
output
signal
coupled
feedforward
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020217017759A
Other languages
English (en)
Korean (ko)
Inventor
데바프리야 사후
리츠 사치데브
Original Assignee
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 텍사스 인스트루먼츠 인코포레이티드 filed Critical 텍사스 인스트루먼츠 인코포레이티드
Publication of KR20210102252A publication Critical patent/KR20210102252A/ko
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
KR1020217017759A 2018-12-13 2019-12-11 직접 피드포워드 회로를 갖는 위상 고정 루프(pll) Pending KR20210102252A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/219,067 US10924123B2 (en) 2018-12-13 2018-12-13 Phase-locked loop (PLL) with direct feedforward circuit
US16/219,067 2018-12-13
PCT/US2019/065611 WO2020123587A1 (en) 2018-12-13 2019-12-11 Phase-locked loop (pll) with direct feedforward circuit

Publications (1)

Publication Number Publication Date
KR20210102252A true KR20210102252A (ko) 2021-08-19

Family

ID=71073070

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020217017759A Pending KR20210102252A (ko) 2018-12-13 2019-12-11 직접 피드포워드 회로를 갖는 위상 고정 루프(pll)

Country Status (6)

Country Link
US (4) US10924123B2 (https=)
EP (1) EP3895319B1 (https=)
JP (1) JP2022514233A (https=)
KR (1) KR20210102252A (https=)
CN (2) CN119853675A (https=)
WO (1) WO2020123587A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10924123B2 (en) 2018-12-13 2021-02-16 Texas Instruments Incorporated Phase-locked loop (PLL) with direct feedforward circuit
US11095293B1 (en) * 2020-12-31 2021-08-17 Texas Instruments Incorporated Low-power fractional analog PLL without feedback divider
US11558057B1 (en) 2021-11-04 2023-01-17 International Business Machines Corporation Phase locked loop pulse truncation

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4305045A (en) 1979-11-14 1981-12-08 Bell Telephone Laboratories, Incorporated Phase locked loop clock synchronizing circuit with programmable controller
JP2778421B2 (ja) * 1993-09-07 1998-07-23 日本電気株式会社 チャージポンプ型位相同期ループ
US5663685A (en) * 1996-03-29 1997-09-02 Bull Hn Information Systems Inc. Dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction
WO2002005428A2 (en) * 2000-07-10 2002-01-17 Silicon Laboratories, Inc. Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
US20020176188A1 (en) * 2001-05-25 2002-11-28 Infineon Technologies N.A. Inc. Offset cancellation of charge pump based phase detector
US6529084B1 (en) 2001-10-11 2003-03-04 International Business Machines Corporation Interleaved feedforward VCO and PLL
JP4220828B2 (ja) * 2003-04-25 2009-02-04 パナソニック株式会社 低域ろ波回路、フィードバックシステムおよび半導体集積回路
DE60314415T2 (de) * 2003-08-29 2008-02-21 Texas Instruments Inc., Dallas Phasenregelschleife mit einer Ladungspumpe und Störunterdrückungsverbesserung der Stromversorgung
KR100568538B1 (ko) * 2004-04-09 2006-04-07 삼성전자주식회사 자기 바이어스 위상 동기 루프
JP3939715B2 (ja) * 2004-08-20 2007-07-04 日本テキサス・インスツルメンツ株式会社 位相同期ループ回路
US7345550B2 (en) * 2005-12-05 2008-03-18 Sirific Wireless Corporation Type II phase locked loop using dual path and dual varactors to reduce loop filter components
US7548123B2 (en) * 2007-07-13 2009-06-16 Silicon Laboratories Inc. Dividerless PLL architecture
US8854094B2 (en) * 2008-03-21 2014-10-07 Broadcom Corporation Phase locked loop
JP5738749B2 (ja) * 2011-12-15 2015-06-24 ルネサスエレクトロニクス株式会社 Ｐｌｌ回路
US8487677B1 (en) * 2012-03-30 2013-07-16 Freescale Semiconductor, Inc. Phase locked loop with adaptive biasing
US9094028B2 (en) 2012-04-11 2015-07-28 Rambus Inc. Wide range frequency synthesizer with quadrature generation and spur cancellation
KR101904749B1 (ko) 2012-05-10 2018-10-08 삼성전자주식회사 위상 고정 루프의 스위칭 및 위상 잡음 향상 기법을 적용한 트랜시버
JP6148953B2 (ja) * 2013-09-26 2017-06-14 日本電波工業株式会社 Ｐｌｌ回路
US10924123B2 (en) * 2018-12-13 2021-02-16 Texas Instruments Incorporated Phase-locked loop (PLL) with direct feedforward circuit

Also Published As

Publication number Publication date
EP3895319A4 (en) 2022-01-26
EP3895319A1 (en) 2021-10-20
US20200195257A1 (en) 2020-06-18
EP3895319B1 (en) 2025-06-11
JP2022514233A (ja) 2022-02-10
US20230396259A1 (en) 2023-12-07
CN112840569B (zh) 2024-12-31
US11777507B2 (en) 2023-10-03
CN112840569A (zh) 2021-05-25
CN119853675A (zh) 2025-04-18
US11418201B2 (en) 2022-08-16
US12334939B2 (en) 2025-06-17
US20210135675A1 (en) 2021-05-06
US20220360269A1 (en) 2022-11-10
US10924123B2 (en) 2021-02-16
WO2020123587A1 (en) 2020-06-18

Similar Documents

Publication Publication Date Title
Lee et al. Jitter transfer characteristics of delay-locked loops-theories and design techniques
US12334939B2 (en) Phase-locked loop (PLL) with direct feedforward circuit
JP4384036B2 (ja) 直接ディジタルチューニングを使用する電圧制御発振器の注入ロックのための方法と装置
EP2974026B1 (en) Ring oscillator circuit and method
US7719365B2 (en) Method and apparatus for reducing silicon area of a phase lock loop (PLL) filter without a noise penalty
CN112242842B (zh) 包括子采样电路的锁相环（pll）电路和时钟发生器
US8854094B2 (en) Phase locked loop
JP5844795B2 (ja) 発振周波数調整装置、発振周波数調整方法及び無線通信装置
JPH02244820A (ja) Ｐｌｌ回路
US10396806B1 (en) Voltage regulator based loop filter for loop circuit and loop filtering method
KR100965764B1 (ko) 위상고정루프 및 그 제어방법
JP2008306331A (ja) 半導体集積回路装置
CN101753138B (zh) 双环路频率综合器及其相位噪声分析方法
US11489532B2 (en) Analog phase locked loop
US6727736B1 (en) Voltage control oscillator noise reduction technique and method thereof
KR101007391B1 (ko) 위상 고정 루프의 위상 잡음 개선 장치 및 방법
CN113595548B (zh) 自适应调节带宽的锁相装置及系统
KR100970916B1 (ko) 위상 동기 루프의 루프-필터의 튜닝
JP4327144B2 (ja) Ｐｌｌ回路におけるアクティブフィルタ。
US20050110534A1 (en) Variation of effective filter capacitance in phase lock loop circuit loop filters
JP4815572B2 (ja) 補償された高速ｐｌｌ回路
KR100987072B1 (ko) 위상 고정 루프의 위상 잡음 개선 장치 및 방법
JPS58154936A (ja) 選局装置
JP2001223580A (ja) 位相同期回路
JPH05328250A (ja) 同期検波回路

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11 Administrative time limit extension requested

Free format text: ST27 STATUS EVENT CODE: U-3-3-T10-T11-OTH-X000 (AS PROVIDED BY THE NATIONAL OFFICE)

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11 Administrative time limit extension requested

Free format text: ST27 STATUS EVENT CODE: U-3-3-T10-T11-OTH-X000 (AS PROVIDED BY THE NATIONAL OFFICE)

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11 Amendment of application requested

Free format text: ST27 STATUS EVENT CODE: A-2-2-P10-P11-NAP-X000 (AS PROVIDED BY THE NATIONAL OFFICE)

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

D22 Grant of ip right intended

Free format text: ST27 STATUS EVENT CODE: A-1-2-D10-D22-EXM-PE0701 (AS PROVIDED BY THE NATIONAL OFFICE)

PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701