CN112840569B - 具有直接前馈电路的锁相环路(pll) - Google Patents
具有直接前馈电路的锁相环路(pll) Download PDFInfo
- Publication number
- CN112840569B CN112840569B CN201980067472.XA CN201980067472A CN112840569B CN 112840569 B CN112840569 B CN 112840569B CN 201980067472 A CN201980067472 A CN 201980067472A CN 112840569 B CN112840569 B CN 112840569B
- Authority
- CN
- China
- Prior art keywords
- output
- input
- coupled
- integrator
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411890616.0A CN119853675A (zh) | 2018-12-13 | 2019-12-11 | 具有直接前馈电路的锁相环路(pll) |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/219,067 | 2018-12-13 | ||
| US16/219,067 US10924123B2 (en) | 2018-12-13 | 2018-12-13 | Phase-locked loop (PLL) with direct feedforward circuit |
| PCT/US2019/065611 WO2020123587A1 (en) | 2018-12-13 | 2019-12-11 | Phase-locked loop (pll) with direct feedforward circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411890616.0A Division CN119853675A (zh) | 2018-12-13 | 2019-12-11 | 具有直接前馈电路的锁相环路(pll) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112840569A CN112840569A (zh) | 2021-05-25 |
| CN112840569B true CN112840569B (zh) | 2024-12-31 |
Family
ID=71073070
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980067472.XA Active CN112840569B (zh) | 2018-12-13 | 2019-12-11 | 具有直接前馈电路的锁相环路(pll) |
| CN202411890616.0A Pending CN119853675A (zh) | 2018-12-13 | 2019-12-11 | 具有直接前馈电路的锁相环路(pll) |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411890616.0A Pending CN119853675A (zh) | 2018-12-13 | 2019-12-11 | 具有直接前馈电路的锁相环路(pll) |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US10924123B2 (https=) |
| EP (1) | EP3895319B1 (https=) |
| JP (1) | JP2022514233A (https=) |
| KR (1) | KR20210102252A (https=) |
| CN (2) | CN112840569B (https=) |
| WO (1) | WO2020123587A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10924123B2 (en) * | 2018-12-13 | 2021-02-16 | Texas Instruments Incorporated | Phase-locked loop (PLL) with direct feedforward circuit |
| US11095293B1 (en) * | 2020-12-31 | 2021-08-17 | Texas Instruments Incorporated | Low-power fractional analog PLL without feedback divider |
| US11558057B1 (en) | 2021-11-04 | 2023-01-17 | International Business Machines Corporation | Phase locked loop pulse truncation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0779159A (ja) * | 1993-09-07 | 1995-03-20 | Nec Corp | チャージポンプ型位相同期ループ |
| US7345550B2 (en) * | 2005-12-05 | 2008-03-18 | Sirific Wireless Corporation | Type II phase locked loop using dual path and dual varactors to reduce loop filter components |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4305045A (en) | 1979-11-14 | 1981-12-08 | Bell Telephone Laboratories, Incorporated | Phase locked loop clock synchronizing circuit with programmable controller |
| US5663685A (en) * | 1996-03-29 | 1997-09-02 | Bull Hn Information Systems Inc. | Dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction |
| US6630868B2 (en) * | 2000-07-10 | 2003-10-07 | Silicon Laboratories, Inc. | Digitally-synthesized loop filter circuit particularly useful for a phase locked loop |
| US20020176188A1 (en) * | 2001-05-25 | 2002-11-28 | Infineon Technologies N.A. Inc. | Offset cancellation of charge pump based phase detector |
| US6529084B1 (en) | 2001-10-11 | 2003-03-04 | International Business Machines Corporation | Interleaved feedforward VCO and PLL |
| JP4220828B2 (ja) * | 2003-04-25 | 2009-02-04 | パナソニック株式会社 | 低域ろ波回路、フィードバックシステムおよび半導体集積回路 |
| DE60314415T2 (de) * | 2003-08-29 | 2008-02-21 | Texas Instruments Inc., Dallas | Phasenregelschleife mit einer Ladungspumpe und Störunterdrückungsverbesserung der Stromversorgung |
| KR100568538B1 (ko) * | 2004-04-09 | 2006-04-07 | 삼성전자주식회사 | 자기 바이어스 위상 동기 루프 |
| JP3939715B2 (ja) * | 2004-08-20 | 2007-07-04 | 日本テキサス・インスツルメンツ株式会社 | 位相同期ループ回路 |
| US7548123B2 (en) * | 2007-07-13 | 2009-06-16 | Silicon Laboratories Inc. | Dividerless PLL architecture |
| US8854094B2 (en) * | 2008-03-21 | 2014-10-07 | Broadcom Corporation | Phase locked loop |
| JP5738749B2 (ja) * | 2011-12-15 | 2015-06-24 | ルネサスエレクトロニクス株式会社 | Pll回路 |
| US8487677B1 (en) * | 2012-03-30 | 2013-07-16 | Freescale Semiconductor, Inc. | Phase locked loop with adaptive biasing |
| US9094028B2 (en) | 2012-04-11 | 2015-07-28 | Rambus Inc. | Wide range frequency synthesizer with quadrature generation and spur cancellation |
| KR101904749B1 (ko) | 2012-05-10 | 2018-10-08 | 삼성전자주식회사 | 위상 고정 루프의 스위칭 및 위상 잡음 향상 기법을 적용한 트랜시버 |
| JP6148953B2 (ja) * | 2013-09-26 | 2017-06-14 | 日本電波工業株式会社 | Pll回路 |
| US10924123B2 (en) * | 2018-12-13 | 2021-02-16 | Texas Instruments Incorporated | Phase-locked loop (PLL) with direct feedforward circuit |
-
2018
- 2018-12-13 US US16/219,067 patent/US10924123B2/en active Active
-
2019
- 2019-12-11 KR KR1020217017759A patent/KR20210102252A/ko active Pending
- 2019-12-11 WO PCT/US2019/065611 patent/WO2020123587A1/en not_active Ceased
- 2019-12-11 JP JP2021533735A patent/JP2022514233A/ja active Pending
- 2019-12-11 CN CN201980067472.XA patent/CN112840569B/zh active Active
- 2019-12-11 EP EP19895675.7A patent/EP3895319B1/en active Active
- 2019-12-11 CN CN202411890616.0A patent/CN119853675A/zh active Pending
-
2021
- 2021-01-12 US US17/146,510 patent/US11418201B2/en active Active
-
2022
- 2022-07-15 US US17/865,808 patent/US11777507B2/en active Active
-
2023
- 2023-08-18 US US18/452,196 patent/US12334939B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0779159A (ja) * | 1993-09-07 | 1995-03-20 | Nec Corp | チャージポンプ型位相同期ループ |
| US7345550B2 (en) * | 2005-12-05 | 2008-03-18 | Sirific Wireless Corporation | Type II phase locked loop using dual path and dual varactors to reduce loop filter components |
Also Published As
| Publication number | Publication date |
|---|---|
| US20220360269A1 (en) | 2022-11-10 |
| KR20210102252A (ko) | 2021-08-19 |
| US20200195257A1 (en) | 2020-06-18 |
| US11777507B2 (en) | 2023-10-03 |
| US12334939B2 (en) | 2025-06-17 |
| US20230396259A1 (en) | 2023-12-07 |
| EP3895319A1 (en) | 2021-10-20 |
| US11418201B2 (en) | 2022-08-16 |
| US20210135675A1 (en) | 2021-05-06 |
| EP3895319B1 (en) | 2025-06-11 |
| CN119853675A (zh) | 2025-04-18 |
| EP3895319A4 (en) | 2022-01-26 |
| US10924123B2 (en) | 2021-02-16 |
| CN112840569A (zh) | 2021-05-25 |
| WO2020123587A1 (en) | 2020-06-18 |
| JP2022514233A (ja) | 2022-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7078948B2 (en) | Low-pass filter, feedback system, and semiconductor integrated circuit | |
| US12334939B2 (en) | Phase-locked loop (PLL) with direct feedforward circuit | |
| US7719365B2 (en) | Method and apparatus for reducing silicon area of a phase lock loop (PLL) filter without a noise penalty | |
| US8854094B2 (en) | Phase locked loop | |
| US20050088244A1 (en) | Adaptive method and apparatus to control loop bandwidth of a phase lock loop | |
| US8358729B2 (en) | Baseband phase-locked loop | |
| US10396806B1 (en) | Voltage regulator based loop filter for loop circuit and loop filtering method | |
| US7386085B2 (en) | Method and apparatus for high speed signal recovery | |
| CA2632006C (en) | Method and apparatus for capacitance multiplication within a phase locked loop | |
| KR20090067470A (ko) | 위상고정루프 및 그 제어방법 | |
| CN101753138B (zh) | 双环路频率综合器及其相位噪声分析方法 | |
| US20020149087A1 (en) | Semiconductor filter system and signal frequency control method | |
| US7609123B2 (en) | Direct modulation type voltage-controlled oscillator using MOS varicap | |
| US8493115B2 (en) | Phase locked loop circuit and system having the same | |
| US20060267644A1 (en) | Method and apparatus for loop filter size reduction | |
| US7408418B2 (en) | Phase locked loop circuit having reduced lock time | |
| JP4327144B2 (ja) | Pll回路におけるアクティブフィルタ。 | |
| CN113595548B (zh) | 自适应调节带宽的锁相装置及系统 | |
| CN116405023A (zh) | 一种具有极小输出抖动的双vco锁相环电路 | |
| JP2003332907A (ja) | Pll回路、このpll回路を用いたチューナ及び通信システム | |
| JP2004350094A (ja) | Pll回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |