KR20130127013A - 여분-테이퍼형 전이 비아들을 포함하는 반도체 디바이스의 금속화 시스템 - Google Patents

여분-테이퍼형 전이 비아들을 포함하는 반도체 디바이스의 금속화 시스템 Download PDF

Info

Publication number
KR20130127013A
KR20130127013A KR1020117016628A KR20117016628A KR20130127013A KR 20130127013 A KR20130127013 A KR 20130127013A KR 1020117016628 A KR1020117016628 A KR 1020117016628A KR 20117016628 A KR20117016628 A KR 20117016628A KR 20130127013 A KR20130127013 A KR 20130127013A
Authority
KR
South Korea
Prior art keywords
via opening
opening
mask
forming
dielectric material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020117016628A
Other languages
English (en)
Korean (ko)
Inventor
프랑크 포이스텔
토마스 베르너
카이 프로베르그
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
에이엠디 팹 36 리미티드 라이어빌리티 컴퍼니 & 코. 카게
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드, 에이엠디 팹 36 리미티드 라이어빌리티 컴퍼니 & 코. 카게 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20130127013A publication Critical patent/KR20130127013A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020117016628A 2008-12-31 2009-12-29 여분-테이퍼형 전이 비아들을 포함하는 반도체 디바이스의 금속화 시스템 Ceased KR20130127013A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008063430.1 2008-12-31
DE102008063430.1A DE102008063430B4 (de) 2008-12-31 2008-12-31 Verfahren zur Herstellung eines Metallisierungssystem eines Halbleiterbauelements mit zusätzlich verjüngten Übergangskontakten
US12/634,216 US8835303B2 (en) 2008-12-31 2009-12-09 Metallization system of a semiconductor device comprising extra-tapered transition vias
US12/634,216 2009-12-09
PCT/EP2009/009308 WO2010076019A1 (en) 2008-12-31 2009-12-29 A metallization system of a semiconductor device comprising extra-tapered transition vias

Publications (1)

Publication Number Publication Date
KR20130127013A true KR20130127013A (ko) 2013-11-22

Family

ID=42234624

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020117016628A Ceased KR20130127013A (ko) 2008-12-31 2009-12-29 여분-테이퍼형 전이 비아들을 포함하는 반도체 디바이스의 금속화 시스템

Country Status (6)

Country Link
US (1) US8835303B2 (https=)
JP (1) JP2012514319A (https=)
KR (1) KR20130127013A (https=)
CN (1) CN102362343B (https=)
DE (1) DE102008063430B4 (https=)
WO (1) WO2010076019A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9728604B2 (en) 2015-04-09 2017-08-08 Samsung Electronics Co., Ltd. Semiconductor devices
KR20210002324A (ko) * 2019-06-28 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 백엔드 오브 라인 비아와 금속 라인간 마진 개선
US12255134B2 (en) 2019-06-28 2025-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of back end of line via to metal line margin improvement

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2975826A1 (fr) * 2011-05-27 2012-11-30 St Microelectronics Crolles 2 Procede de formation d'un trou ou d'une tranchee ayant un profil evase
JP2013021001A (ja) * 2011-07-07 2013-01-31 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US8987916B2 (en) * 2011-11-28 2015-03-24 Freescale Semiconductor, Inc. Methods and apparatus to improve reliability of isolated vias
JP5891846B2 (ja) * 2012-02-24 2016-03-23 富士通セミコンダクター株式会社 半導体装置の製造方法
US8815752B2 (en) * 2012-11-28 2014-08-26 Micron Technology, Inc. Methods of forming features in semiconductor device structures
US9305886B2 (en) * 2013-12-18 2016-04-05 Globalfoundries Singapore Pte. Ltd. Integrated circuits having crack-stop structures and methods for fabricating the same
US10163778B2 (en) * 2014-08-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of damascene structure
CN104505471B (zh) * 2014-12-22 2017-12-29 昆山工研院新型平板显示技术中心有限公司 一种高开口率掩膜板的制备方法及掩膜板
US9536826B1 (en) * 2015-06-15 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (finFET) device structure with interconnect structure
US9679850B2 (en) * 2015-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company Ltd. Method of fabricating semiconductor structure
US9917027B2 (en) * 2015-12-30 2018-03-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with aluminum via structures and methods for fabricating the same
CN107622992B (zh) * 2016-07-14 2021-04-27 联华电子股份有限公司 半导体元件及其制作方法
US10276485B2 (en) * 2017-08-02 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory
US10998259B2 (en) 2017-08-31 2021-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10522394B2 (en) * 2017-09-25 2019-12-31 Marvell World Trade Ltd. Method of creating aligned vias in ultra-high density integrated circuits
US10566411B2 (en) * 2017-12-07 2020-02-18 Globalfoundries Inc. On-chip resistors with direct wiring connections
KR102751263B1 (ko) 2018-08-07 2025-01-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11158571B2 (en) * 2018-12-20 2021-10-26 Micron Technology, Inc. Devices including conductive interconnect structures, related electronic systems, and related methods
WO2020140202A1 (en) * 2019-01-02 2020-07-09 Yangtze Memory Technologies Co., Ltd. Method for forming dual damascene interconnect structure
US20210020455A1 (en) * 2019-07-17 2021-01-21 Nanya Technology Corporation Conductive via structure
US11652049B2 (en) 2021-03-10 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming thereof
KR20230009126A (ko) * 2021-07-08 2023-01-17 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
KR20230013438A (ko) * 2021-07-19 2023-01-26 삼성전자주식회사 반도체 장치
KR20230135384A (ko) * 2022-03-16 2023-09-25 주식회사 디비하이텍 저항 변화 메모리 장치 및 그 제조 방법
US20240332074A1 (en) * 2023-03-27 2024-10-03 International Business Machines Corporation Metal wires with expanded sidewalls

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
JPH03257822A (ja) * 1990-03-07 1991-11-18 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2787646B2 (ja) * 1992-11-27 1998-08-20 三菱電機株式会社 半導体装置の製造方法
JP3427534B2 (ja) * 1995-01-11 2003-07-22 ソニー株式会社 接続孔の形成方法
JPH10163316A (ja) * 1996-12-04 1998-06-19 Sony Corp 半導体装置における埋め込み配線の形成方法
US6025259A (en) * 1998-07-02 2000-02-15 Advanced Micro Devices, Inc. Dual damascene process using high selectivity boundary layers
US6239017B1 (en) * 1998-09-18 2001-05-29 Industrial Technology Research Institute Dual damascene CMP process with BPSG reflowed contact hole
TW430943B (en) * 1999-01-08 2001-04-21 Nippon Electric Co Method of forming contact or wiring in semiconductor device
JP2000260873A (ja) * 1999-01-08 2000-09-22 Nec Corp 半導体装置のコンタクト又は配線の形成方法
TW424301B (en) * 1999-10-02 2001-03-01 Taiwan Semiconductor Mfg Manufacturing method for dual damascene
JP2001358213A (ja) * 2000-06-13 2001-12-26 Nec Corp テーパ状スルーホールを有する半導体装置の製造方法
US6440847B1 (en) * 2001-04-30 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for forming a via and interconnect in dual damascene
US6861347B2 (en) * 2001-05-17 2005-03-01 Samsung Electronics Co., Ltd. Method for forming metal wiring layer of semiconductor device
KR100386622B1 (ko) * 2001-06-27 2003-06-09 주식회사 하이닉스반도체 듀얼 다마신 배선 형성방법
US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
KR100454128B1 (ko) * 2002-04-02 2004-10-26 삼성전자주식회사 금속간 절연막 패턴 및 그 형성 방법
KR100529676B1 (ko) * 2003-12-31 2005-11-17 동부아남반도체 주식회사 듀얼 다마신 패턴을 형성하는 방법
JP4476171B2 (ja) * 2005-05-30 2010-06-09 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2007149773A (ja) * 2005-11-24 2007-06-14 Mitsumi Electric Co Ltd 半導体装置の製造方法
US8264086B2 (en) * 2005-12-05 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure with improved reliability
DE102006025405B4 (de) * 2006-05-31 2018-03-29 Globalfoundries Inc. Verfahren zur Herstellung einer Metallisierungsschicht eines Halbleiterbauelements mit unterschiedlich dicken Metallleitungen

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9728604B2 (en) 2015-04-09 2017-08-08 Samsung Electronics Co., Ltd. Semiconductor devices
US10217820B2 (en) 2015-04-09 2019-02-26 Samsung Electronics Co., Ltd. Semiconductor devices
US10700164B2 (en) 2015-04-09 2020-06-30 Samsung Electronics Co., Ltd. Semiconductor devices
KR20210002324A (ko) * 2019-06-28 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 백엔드 오브 라인 비아와 금속 라인간 마진 개선
US11276638B2 (en) 2019-06-28 2022-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Back end of line via to metal line margin improvement
US12255134B2 (en) 2019-06-28 2025-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of back end of line via to metal line margin improvement

Also Published As

Publication number Publication date
CN102362343A (zh) 2012-02-22
CN102362343B (zh) 2015-03-25
DE102008063430A1 (de) 2010-07-08
US8835303B2 (en) 2014-09-16
WO2010076019A1 (en) 2010-07-08
US20100164121A1 (en) 2010-07-01
JP2012514319A (ja) 2012-06-21
DE102008063430B4 (de) 2016-11-24

Similar Documents

Publication Publication Date Title
KR20130127013A (ko) 여분-테이퍼형 전이 비아들을 포함하는 반도체 디바이스의 금속화 시스템
US8048796B2 (en) Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material
US8377820B2 (en) Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size
KR100387255B1 (ko) 반도체 소자의 금속 배선 형성 방법
US7214594B2 (en) Method of making semiconductor device using a novel interconnect cladding layer
US20070077761A1 (en) Technique for forming a copper-based metallization layer including a conductive capping layer
US7745327B2 (en) Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime
KR20110003562A (ko) 반도체 디바이스들 내에 비아를 패터닝하는 동안 금속 캡층의 부식을 줄이는 방법
US20030181034A1 (en) Methods for forming vias and trenches with controlled SiC etch rate and selectivity
KR20090045198A (ko) 상호접속 구조물 및 상호접속 구조물의 제조 공정
US20080206986A1 (en) Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime
JP2004228111A (ja) 半導体装置及びその製造方法
CN101228624B (zh) 互连接触的干法回蚀
US20100052175A1 (en) Reducing leakage and dielectric breakdown in dielectric materials of metallization systems of semiconductor devices by forming recesses
TWI251898B (en) Damascene process for fabricating interconnect layers in an integrated circuit
US20090108462A1 (en) Dual integration scheme for low resistance metal layers
US20090294921A1 (en) Semiconductor device comprising metal lines with a selectively formed dielectric cap layer
JP2009027048A (ja) 半導体装置の製造方法
JP2006114724A (ja) 半導体装置及びその製造方法
CN113594133B (zh) 半导体结构及其形成方法
US20100133700A1 (en) Performance enhancement in metallization systems of microstructure devices by incorporating grain size increasing metal features
KR100752174B1 (ko) 2개의 시드층을 이용한 반도체 소자의 구리 배선 형성 방법
KR100788352B1 (ko) 반도체 소자의 구리 배선 형성방법
JP2011171432A (ja) 半導体装置およびその製造方法
KR100789612B1 (ko) 금속 배선 형성 방법

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

A302 Request for accelerated examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000