CN101228624B - 互连接触的干法回蚀 - Google Patents

互连接触的干法回蚀 Download PDF

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CN101228624B
CN101228624B CN2006800270555A CN200680027055A CN101228624B CN 101228624 B CN101228624 B CN 101228624B CN 2006800270555 A CN2006800270555 A CN 2006800270555A CN 200680027055 A CN200680027055 A CN 200680027055A CN 101228624 B CN101228624 B CN 101228624B
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electric conducting
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CN101228624A (zh
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W·布里尔利
S·格雷科
S·桑卡兰
T·斯坦达厄特
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International Business Machines Corp
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Abstract

一种用于具有减小的接触电阻以及改进的可靠性的复合柱体接触接合的方法和结构。使用选择性干法蚀刻，该选择性干法蚀刻包括含氟气体。通过在M1 RIE工艺之后或期间部分地干法回蚀钨接触，来减小接触电阻。接着，随后在M1加衬/电镀工艺期间使凹入的接触金属化。在完全形成后，减少了钨接触的高度。

Description

互连接触的干法回蚀
技术领域
本发明针对半导体器件的制造，尤其针对用于集成电路器件的金属化制造。
背景技术
本发明涉及用于半导体器件的金属化互连的形成，尤其涉及形成在半导体表面上的接触的形成，所述接触与基于铜的金属构成的金属化相接合。在当前实践的工艺中，将本地互连沟槽蚀刻在沉积于具有有源器件的衬底上的第一绝缘层中。该蚀刻的沟槽填充有衬垫/钨核，以与衬底器件的某些部分相接触，并且被抛光成与第一绝缘层共面，以形成本地互连(MC)。
沉积第二绝缘层并且其中蚀刻有柱体(stud)接触孔。该蚀刻的柱体接触孔填充有衬垫/钨核，并且被抛光成与形成埋置在该绝缘层中的柱体接触(CA)的第二绝缘层共面，其中使得所述柱体接触与本地互连(MC)相接触，同时也与该器件的另外部分相接触。接着，通过沉积和减去(subtractive)蚀刻或者通过需要第三层的大马士革工艺形成第一布线层(M1)。此M1布线层与柱体接触(CA)相接触。
发明内容
本发明的第一方面提供了一种制造电子器件的方法，包括如下步骤：提供将在其上形成接触的衬底；提供形成在所述衬底上的氧化物中的包括第一导电材料的导电过孔；在该导电过孔上提供电介质层；在该电介质层上提供氧化物层；在该氧化物层上提供光致抗蚀剂层；在该光致抗蚀剂层中形成开口；使用含氟气体来去除该光致抗蚀剂层以及去除在所述开口中的电介质层和氧化物层以及所述第一导电材料的至少一部分；以及在所述开口中沉积第二导电材料，以形成包括第一导电材料和第二导电材料的复合导电过孔。
本发明能够改善CA(柱体接触)接触电阻增大的问题，其中CA接触电阻随着工艺从90nm节点尺寸发展到65nm和45nm节点尺寸而增大。本发明也能够提供比某些已知器件中的更可靠的接触。
含氟气体优选地是NF3、F2或SF6。在优选实施方式中，电介质层是低K SiCOH材料。此低K SiCOH材料可以是多孔超低K材料。在优选实施方式中，第一导电材料是钨，以及第二导电材料是铜。然而，本发明并不限于使用钨本地互连。在优选实施方式中，含氟气体包括大约500sccm的氩和大约50sccm的NF3。此含氟气体还可以包括在压力为大约100mTorr到大约200mTorr下大约10sccm的O2和50sccm的CH2F2或CH3F。
本发明的第二方面提供了一种制造电子器件的方法，包括如下步骤：提供将在其上形成接触的衬底；提供形成在所述衬底上的氧化物中的包括第一导电材料的导电过孔；在该导电过孔上提供电介质层；在该电介质层上提供氧化物层；在该氧化物层上提供光致抗蚀剂层；在该光致抗蚀剂层中形成开口；使用含碳氟化合物的气体来去除在所述开口中的电介质层和氧化物层；去除光致抗蚀剂层；使用含氟气体来去除在所述开口中第一导电材料的至少一部分；以及在所述开口中沉积第二导电材料，以形成包括第一导电材料和第二导电材料的复合导电过孔。
本发明的另一方面提供了一种制造电子器件的方法，包括如下步骤：提供将在其上形成接触的衬底；提供包括第一导电材料的形成在所述衬底上的氧化物中的导电过孔；在该导电过孔上提供电介质层；在该电介质层上提供氧化物层；在该氧化物层上提供光致抗蚀剂层；在该光致抗蚀剂层中形成开口；使用含碳氟化合物的气体来去除在所述开口中的电介质层和氧化物层；使用含氟气体来去除光致抗蚀剂层和去除在所述开口中的第一导电材料的一部分；在所述开口中沉积第二导电材料，以形成包括第一导电材料和第二导电材料的复合导电过孔。
本发明在另一方面还提供一种电子器件，包括：形成在衬底上的多晶硅栅极；与多晶硅栅极相接触的复合柱体过孔结构，该复合柱体过孔结构具有第一部分和第二部分。在优选实施方式中，第一部分包括钨，以及第二部分包括铜。在优选实施方式中，只有第一部分与多晶硅栅极相接触。在优选实施方式中，复合柱体过孔结构的宽度约为100nm以及高度约为2000埃。第一部分的高度约为500埃。
附图说明
以下通过示例方式，参考附图更加详细地描述本发明的实施方式，其中：
图1-5示出了用于形成柱体接触互连的传统工艺；以及
图6-9示出了根据本发明用于形成柱体接触互连的方法。
附图仅用于说明目的，并未按比例绘制。
具体实施方式
本发明通过在M1 RIE工艺之后或期间部分地干法回蚀钨CA接触，来减小CA接触电阻。接着，随后在M1加衬/电镀工艺期间使凹入的CA接触金属化。在钨CA已经完全形成后，本发明减小了钨CA的高度。减小CA的高度会对CA接触电阻具有显著影响。
例如，考虑在具有TEOS(正硅酸乙酯，Si(OC2H5)4)硬掩膜(HM)的SiCOH材料中的M1。存在一种不蚀刻(或者以非常低的速率蚀刻)TEOS(包括HM和CA TEOS二者)的选择性SiCOH蚀刻化学反应。这种SiCOH蚀刻化学反应是预期容易蚀刻W的基于NF3的蚀刻。
本发明公开了在M1的电介质蚀刻中回蚀，以便降低钨接触电阻。钨的凹入对于随后的金属化不是问题，因为本发明使用能够可靠填充具有高深宽比特征的传统加衬/种子/电镀工艺。
更详细地参考附图，特别是参考图1，其中示出了在氧化物20中的导电过孔(CA)15。在优选实施方式中，导电材料会是钨(W)。现在参考图2，现在可以通过传统大马士革工艺创建下一层金属导线，该工艺开始先沉积低K电介质膜(M1电介质)30，接着沉积氧化物硬掩膜(M1硬掩膜)40和M1光致抗蚀剂50。
现在参考图3，其中示出了通过包含抗蚀剂剥离的反应离子蚀刻(RIE)将M1线图形60转印到电介质30中。现在参考图4，其中示出了传统的加衬/种子/电镀工艺步骤，以便形成衬垫70和M1布线金属80。现在参考图5，其中示出了最后的传统工艺步骤CMP，以形成M1布线90。
本发明可以和与图2所示的低K材料30和氧化物硬掩膜40的电介质沉积步骤相同的步骤，以及与其后紧跟着的光刻步骤相同的步骤一起使用。本发明在RIE步骤期间或之后有别于已有技术。
参考图6，本发明的第一实施方式使用含氟气体(但不是基于碳氟化合物的气体)，诸如NF3，F2或SF6来选择性地蚀刻低K电介质30到氧化物20。在优选实施方式中，低K电介质30是类似于SiCOH的材料，其可以是多孔-ULK(超低K)材料。在该RIE步骤期间，抗蚀剂选择性将会很低，通过在这些基于氟的化学反应中表现出低蚀刻速率的氧化物硬掩膜40来提供这种情况下的临界尺寸(CD)控制。一旦在CA钨15上的低K材料清除，基于氟的化学反应也能够蚀刻CA钨15以及CA衬垫10。因此，低K过蚀刻可以被用于使CA钨过孔凹入至希望的深度。由于在这些化学反应中抗蚀剂的蚀刻速率很高，因此抗蚀剂也可以在低K过蚀刻之前或期间被完全消耗掉，并且不需要额外的抗蚀剂剥离。
此选择性M1 RIE工艺与诸如平行板和中密度等离子体RIE工具的传统蚀刻工具兼容。在优选实施方式中，蚀刻气体包括大约500sccm的Ar和大约50sccm的NF3。另外，可以添加少量的O2和CH2F2或CH3F。例如，大约10sccm的O2和大约50sccm的CH2F2或CH3F。后面的添加物可以帮助维持临界尺寸或者增大对氧化物硬掩膜或抗蚀剂的选择性。在优选实施方式中，压力大约为100到200mTorr，针对27MHz和2MHz的频率，功率均为大约500W。
本发明的另一实施方式是在光刻步骤之后遵照已知技术。换句话说，使用基于碳氟化合物的化学反应来限定沟槽和抗蚀剂剥离，以去除光致抗蚀剂材料。在这点上，可以换成基于氟的化学剂(NF3，F2，SF6)来相对于氧化物硬掩膜20和CA TEOS有选择地使CA钨15和衬垫10凹入。
在本发明的另一实施方式中，在光刻步骤之后遵照已知技术。这种情况下，可以使用基于碳氟化合物的化学反应来限定低K电介质30中的沟槽，但是省略抗蚀剂剥离。下一步骤可以是使CA钨15和衬垫10凹入，这一步骤也剥离了剩余的光致抗蚀剂材料50。
图6示出了最终结果的横截面。图7示出了针对这三个实施方式的俯视图，其示出了位于形成在低K电介质30和氧化物硬掩膜40中的凹入沟槽中的部分暴露的CA钨15和衬垫10。此结构的金属化通过上面讨论的已知技术来实现。
参考图8，其中示出了在衬垫70和M1布线金属80的加衬/种子/电镀之后的结构。参考图9，示出了CMP之后的结构。
通过对比图5和图9，可以理解本发明的新颖特征。CA已经被直接凹入M1线之下，并且CA柱体中钨体积15相当大的部分已经被铜80代替。铜80的低电阻率导致了较低的柱体电阻。另外，利用该新结构，在CA柱体15与M1线80之间的接触区域明显更大并且可以产生更可靠接合。这提供了到器件的接合保持不变并且材料相同(阻挡层和W)的显著的可靠性优点。
如图9所示，现在CA柱体互连是具有两种导电材料的复合结构。在优选实施方式中，导电材料是钨和铜。在优选实施方式中，此复合柱体结构的宽度大约为100nm以及高度约为2000埃，并且钨部分的高度约为500埃。
此复合CA柱体接触将具有比传统接触更低的接触电阻。例如，2000埃高以及95nm宽的传统钨CA柱体估计其接触电阻为19欧姆。该电阻的大约三分之一来自于W的导电性。如果钨CA被回蚀为500埃的高度，则接触电阻将从19欧姆降为13欧姆。另一优点是增大在任何未对准(以及凹入的)CA柱体与M1线之间的接触区域。除了铜线与CA柱体之间较低的接触电阻之外，这也提供了更可靠的接触。
对于与本公开相关的本领域技术人员来说，很明显的是，可以在不脱离本发明精神的条件下做出除此处特别描述的那些实施方式之外本发明的其他修改。因此，这种修改都被视为在由所附权利要求限定的本发明的范围之内。

Claims (26)

1.一种制造电子器件的方法，包括如下步骤：
提供将在其上形成接触的衬底；
提供形成在所述衬底上的氧化物中的包括第一导电材料的导电过孔；
在所述导电过孔上提供电介质层；
在所述电介质层上提供氧化物硬掩膜；
在所述氧化物硬掩膜上提供光致抗蚀剂层；
在所述光致抗蚀剂层中形成开口；
使用除基于碳氟化合物的气体之外的含氟气体来去除所述光致抗蚀剂层以及去除在所述开口中的所述电介质层和所述氧化物硬掩膜以及所述第一导电材料的一部分；
在所述开口中沉积第二导电材料，以形成包括所述第一导电材料和所述第二导电材料的复合导电过孔。
2.根据权利要求1所述的方法，其中所述含氟气体选自由NF3、F2和SF6组成的组。
3.根据权利要求1所述的方法，其中所述电介质层是低K SiCOH材料。
4.根据权利要求3所述的方法，其中所述低K SiCOH材料是多孔超低K材料。
5.根据权利要求1所述的方法，其中所述第一导电材料是钨，以及所述第二导电材料是铜。
6.根据权利要求2所述的方法，其中所述含氟气体包括500sccm的氩以及50sccm的NF3。
7.根据权利要求6所述的方法，其中所述含氟气体的压力是100mTorr到200mTorr。
8.一种制造电子器件的方法，包括如下步骤：
提供将在其上形成接触的衬底；
提供形成在所述衬底上的氧化物中的包括第一导电材料的导电过孔；
在所述导电过孔上提供电介质层；
在所述电介质层上提供氧化物硬掩膜；
在所述氧化物硬掩膜上提供光致抗蚀剂层；
在所述光致抗蚀剂层中形成开口；
使用含碳氟化合物的气体来去除在所述开口中的所述电介质层和所述氧化物硬掩膜以及去除所述光致抗蚀剂层；
使用除基于碳氟化合物的气体之外的含氟气体来去除在所述开口中的所述第一导电材料的一部分；
在所述开口中沉积第二导电材料，以形成包括所述第一导电材料和所述第二导电材料的复合导电过孔。
9.根据权利要求8所述的方法，其中所述含氟气体选自由NF3、F2和SF6组成的组。
10.根据权利要求8所述的方法，其中所述电介质层是低KSiCOH材料。
11.根据权利要求10所述的方法，其中所述低K SiCOH材料是多孔超低K材料。
12.根据权利要求8所述的方法，其中所述第一导电材料是钨，以及所述第二导电材料是铜。
13.根据权利要求9所述的方法，其中所述含氟气体包括500sccm的氩以及50sccm的NF3。
14.根据权利要求13所述的方法，其中所述含氟气体的压力是100mTorr到200mTorr。
15.一种制造电子器件的方法，包括如下步骤：
提供将在其上形成接触的衬底；
提供形成在所述衬底上的氧化物中的包括第一导电材料的导电过孔；
在所述导电过孔上提供电介质层；
在所述电介质层上提供氧化物硬掩膜；
在所述氧化物硬掩膜上提供光致抗蚀剂层；
在所述光致抗蚀剂层中形成开口；
使用含碳氟化合物的气体来去除在所述开口中的所述电介质层和所述氧化物硬掩膜；
使用除基于碳氟化合物的气体之外的含氟气体来去除所述光致抗蚀剂层和去除在所述开口中的所述第一导电材料的一部分；
在所述开口中沉积第二导电材料，以形成包括所述第一导电材料和所述第二导电材料的复合导电过孔。
16.根据权利要求15所述的方法，其中所述含氟气体选自由NF3、F2和SF6组成的组。
17.根据权利要求15所述的方法，其中所述电介质层是低KSiCOH材料。
18.根据权利要求17所述的方法，其中所述低K SiCOH材料是多孔超低K材料。
19.根据权利要求15所述的方法，其中所述第一导电材料是钨，以及所述第二导电材料是铜。
20.根据权利要求16所述的方法，其中所述含氟气体包括500sccm的氩以及50sccm的NF3。
21.根据权利要求20所述的方法，其中所述含氟气体的压力是100mTorr到200mTorr。
22.一种电子器件，包括：
形成在衬底上的多晶硅栅极；
与所述多晶硅栅极相接触的复合柱体过孔结构，所述复合柱体过孔结构具有第一部分和第二部分，
其中所述第一部分位于所述第二部分的下部和部分侧部，并且
其中所述第一部分与所述多晶硅栅极和导电金属互连相接触。
23.根据权利要求22所述的电子器件，其中所述第一部分由钨组成，所述第二部分由铜组成。
24.根据权利要求23所述的电子器件，其中只有所述第一部分与所述多晶硅栅极相接触。
25.根据权利要求24所述的电子器件，其中所述复合柱体过孔结构的宽度为100nm以及高度为2000埃。
26.根据权利要求24所述的电子器件，其中所述第一部分的高度为500埃。
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