KR20100053446A - 반도체 장치 및 반도체 장치의 제조 방법 - Google Patents
반도체 장치 및 반도체 장치의 제조 방법 Download PDFInfo
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- KR20100053446A KR20100053446A KR1020090107420A KR20090107420A KR20100053446A KR 20100053446 A KR20100053446 A KR 20100053446A KR 1020090107420 A KR1020090107420 A KR 1020090107420A KR 20090107420 A KR20090107420 A KR 20090107420A KR 20100053446 A KR20100053446 A KR 20100053446A
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Abstract
Description
Claims (10)
- 복수의 반도체 기판의 각각이 갖는 패드 형성면의 연결 전극 패드가 배선에 의해 전기적으로 접속되는 형태로 상기 복수의 반도체 기판을 적층시킨 반도체 장치로서,하층이 되는 상기 반도체 기판의 패드 형성면에는, 중계 배선에 의해 그 연결 전극 패드와 접속된 중계 전극 패드가, 상층이 되는 상기 반도체 기판에 노출되는 형태로 추가로 구비되고,상기 복수의 반도체 기판이 실장되는 실장면의 실장 전극 패드와 상기 하층의 연결 전극 패드가 배선에 의해 전기적으로 접속됨과 함께, 상기 상층의 연결 전극 패드와 상기 하층의 중계 전극 패드가 배선에 의해 전기적으로 접속되는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,복수의 제1 반도체 기판의 각각이 갖는 패드 형성면의 제1 연결 전극 패드가 상기 패드 형성면의 법선 방향(normal direction)으로 노출되고, 그리고 연결 전극 패드에 연결된 상기 중계 전극 패드를 갖는 중계용 기판이 최상층이 되는 형태로 상기 복수의 제1 반도체 기판과 상기 중계용 기판이 적층됨과 함께, 상기 중계용 기판의 연결 전극 패드와 상기 각 제1 연결 전극 패드가 하층 배선으로 상기 실장 전극 패드에 연결된 제1 블록과,복수의 제2 반도체 기판의 각각이 갖는 패드 형성면의 제2 연결 전극 패드가 상기 패드 형성면의 법선 방향으로 노출되는 형태로 상기 복수의 제2 반도체 기판이 적층됨과 함께, 상기 각 제2 연결 전극 패드가 상층 배선으로 연결된 제2 블록을 구비하고,상기 제2 블록에 있어서의 최하층의 반도체 기판이 상기 중계용 기판의 연결 전극 패드를 덮고, 그리고 상기 중계 전극 패드를 노출하는 형태로, 상기 제2 블록이 상기 제1 블록에 적층되어, 상기 중계 전극 패드와 상기 제2 연결 전극 패드가 상기 상층 배선에 의해 연결되는 반도체 장치.
- 제2항에 있어서,상기 상층의 패드 형성면과 상기 하층의 패드 형성면과의 사이의 단차(stepped difference)를 완화하는 형태로 각 패드 형성면을 연결하는 연속면을 가진 절연성의 경사부를 구비하고,상기 상층 배선 및 상기 하층 배선은,상기 상층의 연결 전극 패드와 상기 하층의 연결 전극 패드와의 사이를 연결하여 상기 연속면에 적층된 금속막인 반도체 장치.
- 제1항 내지 제3항 중 어느 한 항에 있어서,상기 중계 배선이 절연층을 사이에 끼우는 다층 구조로 형성되는 반도체 장치.
- 복수의 반도체 기판의 각각이 갖는 패드 형성면의 연결 전극 패드가 배선에 의해 전기적으로 접속되는 형태로 상기 복수의 반도체 기판이 적층되는 반도체 장치의 제조 방법으로서,하층이 되는 상기 반도체 기판의 패드 형성면에, 중계 배선에 의해 그 연결 전극 패드와 접속된 중계 전극 패드가 형성된 후, 상층이 되는 상기 반도체 기판이 상기 중계 전극 패드를 노출하는 형태로 상기 하층에 적층되는 공정과,상기 복수의 반도체 기판이 실장되는 실장면의 실장 전극 패드와 상기 하층의 연결 전극 패드를 전기적으로 접속하는 배선이 형성되는 공정과,상기 하층에 상기 상층이 적층되고 나서, 상기 상층의 연결 전극 패드와 상기 하층의 중계 전극 패드를 연결하는 배선이 형성되는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제5항에 있어서,복수의 제1 반도체 기판의 각각이 갖는 패드 형성면의 제1 연결 전극 패드가 상기 패드 형성면의 법선 방향으로 노출되고, 그리고 연결 전극 패드에 연결된 상기 중계 전극 패드를 갖는 중계용 기판이 최상층이 되는 형태로 상기 복수의 제1 반도체 기판과 상기 중계용 기판이 적층됨과 함께, 상기 중계용 기판의 연결 전극 패드와 상기 각 제1 연결 전극 패드가 하층 배선으로 상기 실장 전극 패드에 연결됨으로써 제1 블록이 형성되고,복수의 제2 반도체 기판의 각각이 갖는 패드 형성면의 제2 연결 전극 패드가 상기 패드 형성면의 법선 방향으로 노출되는 형태로 상기 복수의 제2 반도체 기판이 적층됨과 함께, 상기 각 제2 연결 전극 패드가 상층 배선으로 연결됨으로써 제2 블록이 형성되고,상기 제2 블록에 있어서의 최하층의 반도체 기판이 상기 중계용 기판의 연결 전극 패드를 덮고, 그리고 상기 중계 전극 패드를 노출하는 형태로, 상기 제2 블록이 상기 제1 블록에 적층되어, 상기 중계 전극 패드와 상기 제2 연결 전극 패드가 상기 상층 배선에 의해 연결되는 반도체 장치의 제조 방법.
- 제6항에 있어서,상기 상층의 패드 형성면과 상기 하층의 패드 형성면과의 사이의 단차를 완화하는 형태로 각 패드 형성면을 연결하는 연속면을 가진 절연성의 경사부가 형성되고,상기 상층의 연결 전극 패드와 상기 하층의 연결 전극 패드와의 사이가 상기 연속면을 통하여 연결되는 형태로 도전성 미립자를 포함하는 액상체가 토출되고, 상기 액상체가 건조하여 소성됨으로써, 상기 연결 전극 패드간을 연결하는 상기 배선이 형성되는 반도체 장치의 제조 방법.
- 제5항 내지 제7항 중 어느 한 항에 있어서,상기 연결 전극 패드와 상기 중계 전극 패드와의 사이가 연결되는 형태로, 도전성 미립자를 포함하는 액상체가 토출되고, 상기 액상체가 건조하여 소성됨으로써, 상기 중계 배선이 형성되는 반도체 장치의 제조 방법.
- 제5항 내지 제8항 중 어느 한 항에 있어서,상기 중계 배선이 절연층을 사이에 끼우는 다층 구조로 형성되는 반도체 장치의 제조 방법.
- 제9항에 있어서,절연층 형성 재료가 포함되는 액상체가 상기 패드 형성면을 향하여 토출되고, 상기 액상체가 건조함으로써, 상기 절연층이 형성되는 반도체 장치의 제조 방법.
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103098206A (zh) * | 2010-03-18 | 2013-05-08 | 莫塞德技术公司 | 具有偏移裸片叠层的多芯片封装及其制造方法 |
JP5289484B2 (ja) | 2011-03-04 | 2013-09-11 | 株式会社東芝 | 積層型半導体装置の製造方法 |
US9230942B2 (en) | 2013-02-26 | 2016-01-05 | Sandisk Information Technology (Shanghai) Co., Ltd. | Semiconductor device including alternating stepped semiconductor die stacks |
KR102222484B1 (ko) * | 2014-05-27 | 2021-03-04 | 에스케이하이닉스 주식회사 | 윙부를 가지는 플렉시블 적층 패키지 |
CN106717135B (zh) * | 2014-09-24 | 2019-09-27 | 皇家飞利浦有限公司 | 印刷电路板和印刷电路板布置 |
US10262926B2 (en) * | 2016-10-05 | 2019-04-16 | Nexperia B.V. | Reversible semiconductor die |
JP2021089932A (ja) | 2019-12-03 | 2021-06-10 | キオクシア株式会社 | 半導体記憶装置 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5675180A (en) * | 1994-06-23 | 1997-10-07 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
JP3769997B2 (ja) | 1999-09-22 | 2006-04-26 | セイコーエプソン株式会社 | マルチチップパッケージの製造方法 |
JP3471270B2 (ja) * | 1999-12-20 | 2003-12-02 | Necエレクトロニクス株式会社 | 半導体装置 |
JP2001196529A (ja) * | 2000-01-17 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置及びその配線方法 |
NO20001360D0 (no) | 2000-03-15 | 2000-03-15 | Thin Film Electronics Asa | Vertikale elektriske forbindelser i stabel |
JP2001291821A (ja) | 2000-04-07 | 2001-10-19 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6359340B1 (en) * | 2000-07-28 | 2002-03-19 | Advanced Semiconductor Engineering, Inc. | Multichip module having a stacked chip arrangement |
JP3660918B2 (ja) * | 2001-07-04 | 2005-06-15 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP2003023135A (ja) * | 2001-07-06 | 2003-01-24 | Sharp Corp | 半導体集積回路装置 |
US6747348B2 (en) * | 2001-10-16 | 2004-06-08 | Micron Technology, Inc. | Apparatus and method for leadless packaging of semiconductor devices |
JP3918936B2 (ja) | 2003-03-13 | 2007-05-23 | セイコーエプソン株式会社 | 電子装置及びその製造方法、回路基板並びに電子機器 |
TW588446B (en) * | 2003-03-21 | 2004-05-21 | Advanced Semiconductor Eng | Multi-chips stacked package |
JP4327657B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
US7208345B2 (en) | 2005-05-11 | 2007-04-24 | Infineon Technologies Ag | Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device |
US20060267173A1 (en) * | 2005-05-26 | 2006-11-30 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
US7728411B2 (en) * | 2006-02-15 | 2010-06-01 | Sandisk Corporation | COL-TSOP with nonconductive material for reducing package capacitance |
KR100800149B1 (ko) * | 2006-06-30 | 2008-02-01 | 주식회사 하이닉스반도체 | 스택 패키지 |
US8242607B2 (en) * | 2006-12-20 | 2012-08-14 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die and method of manufacture thereof |
JP4799479B2 (ja) * | 2007-05-14 | 2011-10-26 | Okiセミコンダクタ株式会社 | マルチチップパッケージ |
US8723332B2 (en) * | 2007-06-11 | 2014-05-13 | Invensas Corporation | Electrically interconnected stacked die assemblies |
US20090051043A1 (en) * | 2007-08-21 | 2009-02-26 | Spansion Llc | Die stacking in multi-die stacks using die support mechanisms |
US7906853B2 (en) * | 2007-09-06 | 2011-03-15 | Micron Technology, Inc. | Package structure for multiple die stack |
JP2009094432A (ja) * | 2007-10-12 | 2009-04-30 | Toshiba Corp | 積層型半導体パッケージの製造方法 |
KR20090055316A (ko) * | 2007-11-28 | 2009-06-02 | 삼성전자주식회사 | 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법 |
JP2009164160A (ja) * | 2007-12-28 | 2009-07-23 | Panasonic Corp | 半導体デバイス積層体および実装方法 |
KR101053140B1 (ko) * | 2009-04-10 | 2011-08-02 | 주식회사 하이닉스반도체 | 적층 반도체 패키지 |
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KR20150087684A (ko) * | 2014-01-22 | 2015-07-30 | 엘지이노텍 주식회사 | 회로기판 및 반도체 패키지 |
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US20100117241A1 (en) | 2010-05-13 |
US8274142B2 (en) | 2012-09-25 |
KR101119031B1 (ko) | 2012-03-16 |
JP2010118395A (ja) | 2010-05-27 |
JP5126002B2 (ja) | 2013-01-23 |
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