KR20090012136A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR20090012136A
KR20090012136A KR1020080072364A KR20080072364A KR20090012136A KR 20090012136 A KR20090012136 A KR 20090012136A KR 1020080072364 A KR1020080072364 A KR 1020080072364A KR 20080072364 A KR20080072364 A KR 20080072364A KR 20090012136 A KR20090012136 A KR 20090012136A
Authority
KR
South Korea
Prior art keywords
wiring
layer
standard cell
power supply
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020080072364A
Other languages
English (en)
Korean (ko)
Inventor
노부히로 쯔다
Original Assignee
가부시끼가이샤 르네사스 테크놀로지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 르네사스 테크놀로지 filed Critical 가부시끼가이샤 르네사스 테크놀로지
Publication of KR20090012136A publication Critical patent/KR20090012136A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020080072364A 2007-07-25 2008-07-24 반도체 장치 Ceased KR20090012136A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2007-00193580 2007-07-25
JP2007193580 2007-07-25
JP2008137063A JP5293939B2 (ja) 2007-07-25 2008-05-26 半導体装置
JPJP-P-2008-00137063 2008-05-26

Publications (1)

Publication Number Publication Date
KR20090012136A true KR20090012136A (ko) 2009-02-02

Family

ID=40477685

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080072364A Ceased KR20090012136A (ko) 2007-07-25 2008-07-24 반도체 장치

Country Status (4)

Country Link
JP (1) JP5293939B2 (https=)
KR (1) KR20090012136A (https=)
CN (1) CN101388391B (https=)
TW (1) TWI437665B (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101429396B1 (ko) * 2013-01-28 2014-08-11 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 표준 셀 디자인 레이아웃
KR20150145181A (ko) * 2014-06-18 2015-12-29 에이알엠 리미티드 집적회로 내부의 비아 배치
KR20150145178A (ko) * 2014-06-18 2015-12-29 에이알엠 리미티드 집적회로 내부의 전력망 도체 배치

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5552775B2 (ja) 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
JP5685457B2 (ja) * 2010-04-02 2015-03-18 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JPWO2013018589A1 (ja) * 2011-08-01 2015-03-05 国立大学法人電気通信大学 半導体集積回路装置
CN103546146B (zh) * 2013-09-24 2016-03-02 中国科学院微电子研究所 抗单粒子瞬态脉冲cmos电路
JP5776802B2 (ja) * 2014-02-14 2015-09-09 ソニー株式会社 半導体集積回路
US11120190B2 (en) * 2017-11-21 2021-09-14 Advanced Micro Devices, Inc. Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
JP7140994B2 (ja) * 2018-08-28 2022-09-22 株式会社ソシオネクスト 半導体集積回路装置
CN112771655B (zh) * 2018-09-28 2024-08-20 株式会社索思未来 半导体集成电路装置以及半导体封装件构造
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
JP7525802B2 (ja) 2020-03-27 2024-07-31 株式会社ソシオネクスト 半導体集積回路装置
CN114492283B (zh) * 2020-11-11 2025-08-01 Oppo广东移动通信有限公司 配置芯片的方法及装置、设备、存储介质
US12575177B2 (en) 2022-09-02 2026-03-10 Changxin Memory Technologies, Inc. Layout structure, semiconductor structure and memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923060A (en) * 1996-09-27 1999-07-13 In-Chip Systems, Inc. Reduced area gate array cell design based on shifted placement of alternate rows of cells
JP3672788B2 (ja) * 2000-02-24 2005-07-20 松下電器産業株式会社 半導体装置のセルレイアウト構造およびレイアウト設計方法
JP3718687B2 (ja) * 2002-07-09 2005-11-24 独立行政法人 宇宙航空研究開発機構 インバータ、半導体論理回路、スタティックランダムアクセスメモリ、及びデータラッチ回路
JP4820542B2 (ja) * 2004-09-30 2011-11-24 パナソニック株式会社 半導体集積回路

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101429396B1 (ko) * 2013-01-28 2014-08-11 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 표준 셀 디자인 레이아웃
US8813016B1 (en) 2013-01-28 2014-08-19 Taiwan Semiconductor Manufacturing Company Limited Multiple via connections using connectivity rings
US9213795B2 (en) 2013-01-28 2015-12-15 Taiwan Semiconductor Manufacturing Company Limited Multiple via connections using connectivity rings
KR20150145181A (ko) * 2014-06-18 2015-12-29 에이알엠 리미티드 집적회로 내부의 비아 배치
KR20150145178A (ko) * 2014-06-18 2015-12-29 에이알엠 리미티드 집적회로 내부의 전력망 도체 배치

Also Published As

Publication number Publication date
TW200915488A (en) 2009-04-01
CN101388391B (zh) 2012-07-11
JP5293939B2 (ja) 2013-09-18
JP2009049370A (ja) 2009-03-05
CN101388391A (zh) 2009-03-18
TWI437665B (zh) 2014-05-11

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