TWI437665B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI437665B
TWI437665B TW097126596A TW97126596A TWI437665B TW I437665 B TWI437665 B TW I437665B TW 097126596 A TW097126596 A TW 097126596A TW 97126596 A TW97126596 A TW 97126596A TW I437665 B TWI437665 B TW I437665B
Authority
TW
Taiwan
Prior art keywords
wiring
layer
layer wiring
lower layer
upper layer
Prior art date
Application number
TW097126596A
Other languages
English (en)
Chinese (zh)
Other versions
TW200915488A (en
Inventor
津田信浩
Original Assignee
瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW200915488A publication Critical patent/TW200915488A/zh
Application granted granted Critical
Publication of TWI437665B publication Critical patent/TWI437665B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW097126596A 2007-07-25 2008-07-14 半導體裝置 TWI437665B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007193580 2007-07-25
JP2008137063A JP5293939B2 (ja) 2007-07-25 2008-05-26 半導体装置

Publications (2)

Publication Number Publication Date
TW200915488A TW200915488A (en) 2009-04-01
TWI437665B true TWI437665B (zh) 2014-05-11

Family

ID=40477685

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097126596A TWI437665B (zh) 2007-07-25 2008-07-14 半導體裝置

Country Status (4)

Country Link
JP (1) JP5293939B2 (https=)
KR (1) KR20090012136A (https=)
CN (1) CN101388391B (https=)
TW (1) TWI437665B (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5552775B2 (ja) 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
JP5685457B2 (ja) * 2010-04-02 2015-03-18 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JPWO2013018589A1 (ja) * 2011-08-01 2015-03-05 国立大学法人電気通信大学 半導体集積回路装置
US8813016B1 (en) 2013-01-28 2014-08-19 Taiwan Semiconductor Manufacturing Company Limited Multiple via connections using connectivity rings
CN103546146B (zh) * 2013-09-24 2016-03-02 中国科学院微电子研究所 抗单粒子瞬态脉冲cmos电路
JP5776802B2 (ja) * 2014-02-14 2015-09-09 ソニー株式会社 半導体集積回路
US9454633B2 (en) * 2014-06-18 2016-09-27 Arm Limited Via placement within an integrated circuit
US9653413B2 (en) * 2014-06-18 2017-05-16 Arm Limited Power grid conductor placement within an integrated circuit
US11120190B2 (en) * 2017-11-21 2021-09-14 Advanced Micro Devices, Inc. Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
JP7140994B2 (ja) * 2018-08-28 2022-09-22 株式会社ソシオネクスト 半導体集積回路装置
CN112771655B (zh) * 2018-09-28 2024-08-20 株式会社索思未来 半导体集成电路装置以及半导体封装件构造
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
JP7525802B2 (ja) 2020-03-27 2024-07-31 株式会社ソシオネクスト 半導体集積回路装置
CN114492283B (zh) * 2020-11-11 2025-08-01 Oppo广东移动通信有限公司 配置芯片的方法及装置、设备、存储介质
US12575177B2 (en) 2022-09-02 2026-03-10 Changxin Memory Technologies, Inc. Layout structure, semiconductor structure and memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923060A (en) * 1996-09-27 1999-07-13 In-Chip Systems, Inc. Reduced area gate array cell design based on shifted placement of alternate rows of cells
JP3672788B2 (ja) * 2000-02-24 2005-07-20 松下電器産業株式会社 半導体装置のセルレイアウト構造およびレイアウト設計方法
JP3718687B2 (ja) * 2002-07-09 2005-11-24 独立行政法人 宇宙航空研究開発機構 インバータ、半導体論理回路、スタティックランダムアクセスメモリ、及びデータラッチ回路
JP4820542B2 (ja) * 2004-09-30 2011-11-24 パナソニック株式会社 半導体集積回路

Also Published As

Publication number Publication date
TW200915488A (en) 2009-04-01
CN101388391B (zh) 2012-07-11
JP5293939B2 (ja) 2013-09-18
KR20090012136A (ko) 2009-02-02
JP2009049370A (ja) 2009-03-05
CN101388391A (zh) 2009-03-18

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MM4A Annulment or lapse of patent due to non-payment of fees