KR20040035596A - 드라이 에칭 방법 - Google Patents
드라이 에칭 방법 Download PDFInfo
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- KR20040035596A KR20040035596A KR10-2003-7013572A KR20037013572A KR20040035596A KR 20040035596 A KR20040035596 A KR 20040035596A KR 20037013572 A KR20037013572 A KR 20037013572A KR 20040035596 A KR20040035596 A KR 20040035596A
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- Prior art keywords
- gas
- etching
- tungsten
- flow rate
- layer
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- 238000000034 method Methods 0.000 title claims abstract description 76
- 238000001312 dry etching Methods 0.000 title claims description 22
- 238000005530 etching Methods 0.000 claims abstract description 221
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 45
- 230000008569 process Effects 0.000 claims abstract description 42
- 238000001020 plasma etching Methods 0.000 claims abstract description 14
- 229910052721 tungsten Inorganic materials 0.000 claims description 61
- 239000010937 tungsten Substances 0.000 claims description 61
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 57
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 230000008859 change Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 61
- 229920005591 polysilicon Polymers 0.000 abstract description 60
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 239000007789 gas Substances 0.000 description 150
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 230000007423 decrease Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000009467 reduction Effects 0.000 description 8
- 239000001307 helium Substances 0.000 description 5
- 229910052734 helium Inorganic materials 0.000 description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- -1 tungsten nitride Chemical class 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (16)
- 실리콘 상의 텅스텐 실리사이드를 Cl2가스와 O2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정을 갖는 것을 특징으로 하는드라이 에칭 방법.
- 제 1 항에 있어서,또한, 상기 Cl2가스와 O2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정 전에, 실리콘 상의 텅스텐 실리사이드를 Cl2가스와 O2가스를 포함하는 에칭 가스로 에칭하는 공정을 갖는 것을 특징으로 하는드라이 에칭 방법.
- 제 2 항에 있어서,상기 Cl2가스와 O2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정에서, 상기 Cl2가스와 O2가스를 포함하는 에칭 가스로 에칭하는 공정보다 Cl2가스에 대한 O2가스의 유량비(O2가스 유량/Cl2가스 유량)를 증가시키는 것을 특징으로 하는드라이 에칭 방법.
- 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,상기 Cl2가스와 O2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정에서의 에칭 가스 전체에 대한 O2가스의 유량비가 0.2 이상 0.5 이하[0.2≤(O2가스 유량/(Cl2가스 유량+O2가스 유량+NF3가스 유량))≤0.5)인 것을 특징으로 하는드라이 에칭 방법.
- 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,상기 텅스텐 실리사이드를, 인접하는 패턴끼리 근접하여 조밀하게 배치된 부분과, 인접하는 패턴끼리 이간하여 드문드문 배치된 부분을 갖는 패턴으로 에칭하는 것을 특징으로 하는드라이 에칭 방법.
- 실리콘 상의 텅스텐을 N2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정을 갖는 것을 특징으로 하는드라이 에칭 방법.
- 제 6 항에 있어서,상기 에칭 가스가 또한 O2가스를 포함하는 것을 특징으로 하는드라이 에칭 방법.
- 제 6 항 또는 제 7 항에 있어서,또한, 상기 N2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정 전에 실리콘 상의 텅스텐을 Cl2가스와 O2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정을 갖는 것을 특징으로 하는드라이 에칭 방법.
- 실리콘 상의 텅스텐을 O2가스와 NF3가스를 포함하는 에칭 가스로 에칭하는 공정을 갖는 것을 특징으로 하는드라이 에칭 방법.
- 제 6 항 내지 제 9 항 중 어느 한 항에 있어서,질화 실리콘층을 마스크로서 상기 텅스텐을 에칭하는 것을 특징으로 하는드라이 에칭 방법.
- 실리콘 상의 텅스텐을, Cl2가스와 O2가스와 NF3가스를 포함하는 에칭 가스로서, 해당 에칭 가스 전체에 대한 Cl2가스의 유량비가 0보다 크고 0.125 이하[0<(Cl2가스 유량/(C12가스 유량+O2가스 유량+NF3가스 유량))≤0.125]인 에칭 가스로 에칭하는 에칭 공정을 갖는 것을 특징으로 하는드라이 에칭 방법.
- 제 11 항에 있어서,또한, 상기 에칭 가스로 에칭하는 공정 전에, 해당 공정보다 에칭 가스 전체에 대한 Cl2가스의 유량비가 큰 에칭 가스로 실리콘 상의 텅스텐을 에칭하는 전단의 에칭 공정을 갖는 것을 특징으로 하는드라이 에칭 방법.
- 제 12 항에 있어서,피처리 기판이 탑재되는 하부 전극에 고주파 전력을 공급할 수 있도록 구성된 평행 평판형의 플라즈마 에칭 장치에 의해서, 상기 전단의 에칭 공정 및 상기 에칭 공정이 실행되고, 상기 에칭 공정에 있어서 상기 하부 전극에 인가되는 고주파 전력이 상기 전단의 에칭 공정에 있어서 상기 하부 전극에 인가되는 고주파 전력보다도 증가되는 것을 특징으로 하는드라이 에칭 방법.
- 제 12 항 또는 제 13 항에 있어서,상기 전단의 에칭 공정과 상기 에칭 공정을 플라즈마 중 파장이 578 nm 부근인 빛, 또는 파장이 542 nm 부근인 빛을 검출하고 이 검출광의 변화에 근거하여 실행하는 것을 특징으로 하는드라이 에칭 방법.
- 제 6 항 내지 제 14 항 중 어느 한 항에 있어서,상기 텅스텐을, 인접하는 패턴끼리 근접하여 조밀하게 배치된 부분과, 인접하는 패턴끼리 이간하여 드문드문 배치된 부분을 갖는 패턴으로 에칭하는 것을 특징으로 하는드라이 에칭 방법.
- 제 6 항 내지 제 15 항 중 어느 한 항에 있어서,상기 실리콘과 상기 텅스텐 사이에 장벽 금속층이 설치되는 것을 특징으로 하는드라이 에칭 방법.
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-2001-00121794 | 2001-04-19 | ||
JP2001121794A JP2002319569A (ja) | 2001-04-19 | 2001-04-19 | ドライエッチング方法 |
JP2001124731 | 2001-04-23 | ||
JPJP-P-2001-00124731 | 2001-04-23 | ||
JP2001364621A JP3986808B2 (ja) | 2001-04-23 | 2001-11-29 | ドライエッチング方法 |
JPJP-P-2001-00364621 | 2001-11-29 | ||
PCT/JP2002/001785 WO2002086957A1 (fr) | 2001-04-19 | 2002-02-27 | Procede de gravure a sec |
Publications (2)
Publication Number | Publication Date |
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KR20040035596A true KR20040035596A (ko) | 2004-04-29 |
KR100593826B1 KR100593826B1 (ko) | 2006-06-28 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020037013572A KR100593826B1 (ko) | 2001-04-19 | 2002-02-27 | 드라이 에칭 방법 |
Country Status (5)
Country | Link |
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US (1) | US7192532B2 (ko) |
KR (1) | KR100593826B1 (ko) |
CN (1) | CN1310293C (ko) |
TW (1) | TWI293092B (ko) |
WO (1) | WO2002086957A1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100771373B1 (ko) * | 2005-11-02 | 2007-10-30 | 동부일렉트로닉스 주식회사 | 반도체 소자의 플라즈마 식각 방법 |
KR101153637B1 (ko) * | 2004-12-24 | 2012-06-18 | 파나소닉 주식회사 | 반도체 칩의 제조 방법 |
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US7988813B2 (en) | 2007-03-12 | 2011-08-02 | Tokyo Electron Limited | Dynamic control of process chemistry for improved within-substrate process uniformity |
US7576018B2 (en) | 2007-03-12 | 2009-08-18 | Tokyo Electron Limited | Method for flexing a substrate during processing |
US7674636B2 (en) | 2007-03-12 | 2010-03-09 | Tokyo Electron Limited | Dynamic temperature backside gas control for improved within-substrate process uniformity |
CN102148146B (zh) * | 2010-02-10 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | 栅极结构形成方法 |
JP6096470B2 (ja) * | 2012-10-29 | 2017-03-15 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
CN103149751B (zh) * | 2013-02-19 | 2015-09-16 | 北京京东方光电科技有限公司 | 一种下部电极及其制作方法 |
JP6289996B2 (ja) * | 2014-05-14 | 2018-03-07 | 東京エレクトロン株式会社 | 被エッチング層をエッチングする方法 |
US9418869B2 (en) * | 2014-07-29 | 2016-08-16 | Lam Research Corporation | Method to etch a tungsten containing layer |
JP6502160B2 (ja) * | 2015-05-11 | 2019-04-17 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
CN112466749B (zh) | 2020-11-16 | 2023-11-14 | 北京北方华创微电子装备有限公司 | 硅片的刻蚀方法 |
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US5164330A (en) * | 1991-04-17 | 1992-11-17 | Intel Corporation | Etchback process for tungsten utilizing a NF3/AR chemistry |
JP3210359B2 (ja) * | 1991-05-29 | 2001-09-17 | 株式会社東芝 | ドライエッチング方法 |
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US5492597A (en) * | 1994-05-13 | 1996-02-20 | Micron Semiconductor, Inc. | Method of etching WSix films |
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US6440870B1 (en) * | 2000-07-12 | 2002-08-27 | Applied Materials, Inc. | Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures |
US6905800B1 (en) * | 2000-11-21 | 2005-06-14 | Stephen Yuen | Etching a substrate in a process zone |
-
2002
- 2002-02-27 US US10/475,268 patent/US7192532B2/en not_active Expired - Lifetime
- 2002-02-27 CN CNB028083849A patent/CN1310293C/zh not_active Expired - Fee Related
- 2002-02-27 WO PCT/JP2002/001785 patent/WO2002086957A1/ja active Application Filing
- 2002-02-27 KR KR1020037013572A patent/KR100593826B1/ko active IP Right Grant
- 2002-03-19 TW TW091105199A patent/TWI293092B/zh not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101153637B1 (ko) * | 2004-12-24 | 2012-06-18 | 파나소닉 주식회사 | 반도체 칩의 제조 방법 |
KR100771373B1 (ko) * | 2005-11-02 | 2007-10-30 | 동부일렉트로닉스 주식회사 | 반도체 소자의 플라즈마 식각 방법 |
Also Published As
Publication number | Publication date |
---|---|
US20050045588A1 (en) | 2005-03-03 |
WO2002086957A1 (fr) | 2002-10-31 |
US7192532B2 (en) | 2007-03-20 |
CN1535473A (zh) | 2004-10-06 |
KR100593826B1 (ko) | 2006-06-28 |
TWI293092B (ko) | 2008-02-01 |
CN1310293C (zh) | 2007-04-11 |
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