KR20040000453A - 자기 조립형 폴리머 막을 구비한 메모리 디바이스 및 그제조 방법 - Google Patents
자기 조립형 폴리머 막을 구비한 메모리 디바이스 및 그제조 방법 Download PDFInfo
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- KR20040000453A KR20040000453A KR10-2003-7014466A KR20037014466A KR20040000453A KR 20040000453 A KR20040000453 A KR 20040000453A KR 20037014466 A KR20037014466 A KR 20037014466A KR 20040000453 A KR20040000453 A KR 20040000453A
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- Prior art keywords
- forming
- polymer
- memory
- polymeric
- dielectric layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5664—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using organic memory material storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
- G11C13/0016—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material comprising polymers
Abstract
Description
Claims (35)
- 트랜지스터들의 어드레스 가능한 어레이와;상기 트랜지스터 어레이를 덮는 유전층과;상기 유전층을 통하여 상기 트랜지스터 어레이에 대해 형성된 복수의 접속부-적어도 몇 개의 접속부들은 노출된다-와;상기 적어도 몇 개의 접속부의 메모리 소자들-상기 메모리 소자들은 오직 상기 접속부 위에만 형성되고, 상기 유전층 위에는 형성되지 않는다-과; 그리고상기 각 메모리 소자들과 접속하는 공통 전극을 포함하는 것을 특징으로 하는 메모리 디바이스.
- 제 1항에 있어서,상기 접속부들은 상기 트랜지스터와 접속하고 상기 유전층을 통해 연장되는 제 1 도전물질로 이루어진 것을 특징으로 하는 메모리 디바이스.
- 제 2항에 있어서,상기 메모리 소자들은 인가되는 전계에 응답하여 저항이 변화하는 물질로 이루어진 것을 특징으로 하는 메모리 디바이스.
- 제 3항에 있어서,상기 물질은 적어도 세개의 다른 저항값 중 하나의 값으로 정해지고 유지될 수 있는 것을 특징으로 하는 메모리 디바이스.
- 제 4항에 있어서,상기 물질은 오직 상기 접속부들에만 점착되고, 상기 유전층에는 점착되지 않는 특성을 갖는 것을 특징으로 하는 메모리 디바이스.
- 제 4항에 있어서,상기 물질은 폴리컨쥬게이션된 폴리머인 것을 특징으로 하는 메모리 디바이스.
- 제 6항에 있어서,상기 폴리컨쥬게이션된 폴리머는 폴리파라페닐렌(polyparaphenylene), 폴리페닐브니엔(polyphenylvenyene), 폴리아닐린(polyaniline) 폴리티오펜(polythiophene), 또는 폴리피롤(polypyrrole) 중 적어도 하나인 것을 특징으로 하는 메모리 디바이스.
- 제 4항에 있어서,상기 물질은 폴리머형 프탈로시아닌(polymeric phtalocyanine)인 것을 특징으로 하는 메모리 디바이스.
- 제 4항에 있어서,상기 물질은 폴리머형 포르피린(polymeric porphyrin)인 것을 특징으로 하는 메모리 디바이스.
- 제 3항에 있어서,상기 접속부들은 상기 트랜지스터로부터 상기 유전체의 표면으로 연장된 도전 플러그와, 상기 도전 플러그의 표면 위의 장벽층과, 그리고 상기 장벽층 위의 점착층을 포함하는 것을 특징으로 하는 메모리 디바이스.
- 제 10항에 있어서,상기 도전 플러그는 알루미늄(aluminum)으로 이루어진 것을 특징으로 하는 특징으로 하는 메모리 디바이스.
- 제 11항에 있어서,상기 장벽층은 텅스텐(tungsten)으로 이루어진 것을 특징으로 하는 메모리 디바이스.
- 제 12항에 있어서,상기 점착층은 구리(copper) 또는 구리 합금(copper alloy)으로 이루어진 것을 특징으로 하는 메모리 디바이스.
- 제 13항에 있어서,상기 물질은 폴리컨쥬게이션된 폴리머인 것을 특징으로 하는 메모리 디바이스.
- 제 13항에 있어서,상기 물질은 폴리머형 프탈로시아닌인 것을 특징으로 하는 메모리 디바이스.
- 제 13항에 있어서,상기 물질은 폴리머형 포르피린인 것을 특징으로 하는 메모리 디바이스.
- 제 13항에 있어서,상기 물질은 폴리컨쥬게이션된 폴리머, 폴리머형 프탈로시아닌, 또는 폴리머형 포르피린 중 적어도 하나인 것을 특징으로 하는 메모리 디바이스.
- 제 17항에 있어서,상기 공통 전극은 알루미늄으로 이루어진 것을 특징으로 하는 메모리 디바이스.
- 메모리 디바이스를 조립하는 방법으로서:트랜지스터의 어레이를 형성하는 단계와;상기 트랜지스터를 유전층으로 덮는 단계와;상기 유전층을 통과하는, 상기 트랜지스터에 대한 도전 접속부를 형성하는 단계와;자기 조립에 의해, 상기 도전 접속부 위에, 다중의 선택 가능한 저항값을 갖는 메모리 소자를 형성하는 단계와; 그리고상기 메모리 소자 위에, 상기 각 메모리 소자에 접속하는 공통 전극을 형성하는 것을 특징으로 하는 방법.
- 제 19항에 있어서,상기 메모리 소자를 형성하는 단계는 오직 상기 도전 접속부에만 점착하고, 상기 유전층에는 점착하지 않는 제1 물질을 증착하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제 20항에 있어서,상기 제1 물질은 폴리컨쥬게이션된 폴리머인 것을 특징으로 하는 방법.
- 제 21항에 있어서,상기 폴리컨쥬게이션된 폴리머는 폴리파라페닐렌, 폴리페닐베니엔, 폴리아닐린, 폴리티오펜, 또는 폴리피롤 중 하나인 것을 특징으로 하는 방법.
- 제 20항에 있어서,상기 제1 물질은 폴리머형 프탈로시아닌인 것을 특징으로 하는 방법.
- 제 20항에 있어서,상기 제1 물질은 폴리머형 포르피린인 것을 특징으로 하는 방법.
- 제 19항에 있어서,상기 도전 접속부를 형성하는 단계는 트랜지스터와 접속하는 바닥부와 그리고 상부를 가진 도전 플러그를 형성하는 단계와, 상기 도전 플러그의 상부 위에 장벽층을 형성하는 단계와, 그리고 상기 장벽층 위에 점착층을 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제 25항에 있어서,상기 메모리 소자를 형성하는 단계는 밀폐된 챔버안에 액체 단량체와 함께 상기 메모리 디바이스를 위치시키는 단계를 포함하는 것을 특징으로 하는 방법.
- 제 26항에 있어서,상기 메모리 소자를 형성하는 단계는 밀폐된 챔버안에 단량체 기체와 함께상기 메모리 디바이스를 위치시키는 단계를 포함하는 것을 특징으로 하는 방법.
- 제 27항에 있어서,상기 액체 단량체 및 상기 단량체 기체는 메틸페닐아세틸렌(methylphenylacetylene)이고, 폴리메틸페닐아세틸렌의 폴리컨쥬게이션된 폴리머가 상기 메모리 소자로서 형성되는 것을 특징으로 하는 방법.
- 제 28항에 있어서,상기 액체 단량체 및 상기 단량체 기체는 테트라시아노벤젠이고, 쿠퍼프탈로시아닌은 상기 메모리 소자로서 형성되는 것을 특징으로 하는 방법.
- 메모리 셀을 형성하는 방법으로서:제1 전극을 형성하는 단계와;자기 조립에 의해 상기 제 1 전극 위에 메모리 소자-상기 메모리 소자는 오직 상기 제1 전극에만 점착하는 폴리머를 포함하고, 상기 폴리머를 전계에 노출시킴으로써 선택 가능한 다중의 저항값을 가진다-를 형성하는 단계와; 그리고상기 메모리 소자 위에 제 2 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제 30항에 있어서,상기 폴리머는 폴리컨쥬게이션된 폴리머인 것을 특징으로 하는 방법.
- 제 31항에 있어서,상기 폴리컨쥬게이션된 폴리머는 폴리파라페닐렌, 폴리페닐베니엔, 폴리아닐린, 폴리티오펜, 또는 폴리피롤 중 하나인 것을 특징으로 하는 방법.
- 제 30항에 있어서,상기 폴리머는 폴리머형 프탈로시아닌인 것을 특징으로 하는 방법.
- 제 30항에 있어서,상기 프탈로시아닌은 쿠퍼프탈로시아닌인 것을 특징으로 하는 방법.
- 제 30항에 있어서,상기 폴리머는 폴리머형 포르피린인 것을 특징으로 하는 방법.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US28905401P | 2001-05-07 | 2001-05-07 | |
US60/289,054 | 2001-05-07 | ||
PCT/US2002/014236 WO2002091384A1 (en) | 2001-05-07 | 2002-05-07 | A memory device with a self-assembled polymer film and method of making the same |
Publications (2)
Publication Number | Publication Date |
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KR20040000453A true KR20040000453A (ko) | 2004-01-03 |
KR100900080B1 KR100900080B1 (ko) | 2009-06-01 |
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KR1020037014466A KR100900080B1 (ko) | 2001-05-07 | 2002-05-07 | 자기 조립형 폴리머 막을 구비한 메모리 디바이스 및 그제조 방법 |
Country Status (7)
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US (2) | US6855977B2 (ko) |
EP (1) | EP1397809B1 (ko) |
JP (1) | JP4886160B2 (ko) |
KR (1) | KR100900080B1 (ko) |
CN (1) | CN100403450C (ko) |
DE (1) | DE60220912T2 (ko) |
WO (1) | WO2002091384A1 (ko) |
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KR100814031B1 (ko) * | 2006-01-13 | 2008-03-17 | 한국과학기술원 | 폴리머 메모리 소자 및 이의 제조 방법 |
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KR100691928B1 (ko) * | 2005-09-16 | 2007-03-09 | 삼성전자주식회사 | 엠보싱 구조물에 의해 형성된 메모리 활성 영역을 포함하는유기 메모리 소자 |
KR100814031B1 (ko) * | 2006-01-13 | 2008-03-17 | 한국과학기술원 | 폴리머 메모리 소자 및 이의 제조 방법 |
Also Published As
Publication number | Publication date |
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CN1513184A (zh) | 2004-07-14 |
US20020163828A1 (en) | 2002-11-07 |
EP1397809A1 (en) | 2004-03-17 |
DE60220912T2 (de) | 2008-02-28 |
JP4886160B2 (ja) | 2012-02-29 |
KR100900080B1 (ko) | 2009-06-01 |
US7295461B1 (en) | 2007-11-13 |
WO2002091384A1 (en) | 2002-11-14 |
JP2004527130A (ja) | 2004-09-02 |
US6855977B2 (en) | 2005-02-15 |
CN100403450C (zh) | 2008-07-16 |
DE60220912D1 (de) | 2007-08-09 |
EP1397809B1 (en) | 2007-06-27 |
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