KR20010089236A - 반도체 집적 회로 장치 및 제조 방법 - Google Patents
반도체 집적 회로 장치 및 제조 방법 Download PDFInfo
- Publication number
- KR20010089236A KR20010089236A KR1020010012207A KR20010012207A KR20010089236A KR 20010089236 A KR20010089236 A KR 20010089236A KR 1020010012207 A KR1020010012207 A KR 1020010012207A KR 20010012207 A KR20010012207 A KR 20010012207A KR 20010089236 A KR20010089236 A KR 20010089236A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- memory
- signal
- test
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 230000015654 memory Effects 0.000 claims abstract description 259
- 238000012360 testing method Methods 0.000 claims abstract description 189
- 238000000034 method Methods 0.000 claims abstract description 64
- 230000008569 process Effects 0.000 claims abstract description 13
- 239000011159 matrix material Substances 0.000 claims description 75
- 230000002950 deficient Effects 0.000 claims description 25
- 230000006870 function Effects 0.000 claims description 25
- 238000013461 design Methods 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 22
- 238000013500 data storage Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 14
- 230000007547 defect Effects 0.000 description 13
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000003068 static effect Effects 0.000 description 5
- 101100386518 Caenorhabditis elegans dbl-1 gene Proteins 0.000 description 4
- 101000823316 Homo sapiens Tyrosine-protein kinase ABL1 Proteins 0.000 description 4
- 101100268653 Leptosphaeria maculans (strain JN3 / isolate v23.1.3 / race Av1-4-5-6-7-8) abl5 gene Proteins 0.000 description 4
- 102100022596 Tyrosine-protein kinase ABL1 Human genes 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
- 210000004556 brain Anatomy 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
Landscapes
- Tests Of Electronic Circuits (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000066335 | 2000-03-10 | ||
| JP2000-066335 | 2000-03-10 | ||
| JP2000364005A JP3980827B2 (ja) | 2000-03-10 | 2000-11-30 | 半導体集積回路装置および製造方法 |
| JP2000-364005 | 2000-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010089236A true KR20010089236A (ko) | 2001-09-29 |
Family
ID=26587168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010012207A Withdrawn KR20010089236A (ko) | 2000-03-10 | 2001-03-09 | 반도체 집적 회로 장치 및 제조 방법 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6601218B2 (enExample) |
| JP (1) | JP3980827B2 (enExample) |
| KR (1) | KR20010089236A (enExample) |
| TW (1) | TW535279B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160119117A (ko) * | 2014-02-07 | 2016-10-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 장치 |
Families Citing this family (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6417695B1 (en) * | 2001-03-15 | 2002-07-09 | Micron Technology, Inc. | Antifuse reroute of dies |
| JP4339534B2 (ja) * | 2001-09-05 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | メモリチップとロジックチップとを搭載し,メモリチップの試験を可能にした半導体装置 |
| US20030149926A1 (en) * | 2002-02-07 | 2003-08-07 | Rajan Krishna B. | Single scan chain in hierarchiacally bisted designs |
| JP3934434B2 (ja) * | 2002-02-19 | 2007-06-20 | 富士通株式会社 | 回路の試験装置 |
| JP2003303499A (ja) * | 2002-04-08 | 2003-10-24 | Mitsubishi Electric Corp | 半導体集積回路 |
| US6925406B2 (en) * | 2002-06-21 | 2005-08-02 | Teseda Corporation | Scan test viewing and analysis tool |
| US6952623B2 (en) * | 2002-07-02 | 2005-10-04 | Texas Instruments, Inc. | Permanent chip ID using FeRAM |
| JP2004047596A (ja) * | 2002-07-10 | 2004-02-12 | Renesas Technology Corp | 半導体装置の製造方法 |
| US7295028B2 (en) * | 2002-08-30 | 2007-11-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit and memory test method |
| US6917215B2 (en) * | 2002-08-30 | 2005-07-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit and memory test method |
| US7096386B2 (en) * | 2002-09-19 | 2006-08-22 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit having functional modules each including a built-in self testing circuit |
| US7007211B1 (en) | 2002-10-04 | 2006-02-28 | Cisco Technology, Inc. | Testing self-repairing memory of a device |
| DE10259282B4 (de) * | 2002-12-18 | 2005-05-19 | Texas Instruments Deutschland Gmbh | Batteriebetriebener Verbrauchszähler mit einem Mikro-Controller und Bausteinen zur Realisierung einer Zustandsmaschine |
| JP4167497B2 (ja) * | 2003-01-17 | 2008-10-15 | 株式会社ルネサステクノロジ | 半導体集積回路及びその試験を行う試験システム |
| WO2004079382A1 (en) * | 2003-03-04 | 2004-09-16 | Koninklijke Philips Electronics N.V. | Automatically detecting and routing of test signals |
| US20040180561A1 (en) * | 2003-03-12 | 2004-09-16 | Nexcleon, Inc. | Structures for testing circuits and methods for fabricating the structures |
| US7308627B2 (en) * | 2003-04-16 | 2007-12-11 | Lsi Corporation | Self-timed reliability and yield vehicle with gated data and clock |
| US6861864B2 (en) * | 2003-04-16 | 2005-03-01 | Lsi Logic Corporation | Self-timed reliability and yield vehicle array |
| JP4308637B2 (ja) * | 2003-12-17 | 2009-08-05 | 株式会社日立製作所 | 半導体試験装置 |
| TWI369504B (en) * | 2004-07-27 | 2012-08-01 | Lsi Corp | Methods of locating a fault within an array of integrated circuits, methods of testing an array of interconnect modules, and speed fault test vehicles for locating a fault within an array of interconnect modules |
| US7284213B2 (en) * | 2005-04-08 | 2007-10-16 | Lsi Corporation | Defect analysis using a yield vehicle |
| US7370257B2 (en) * | 2005-04-08 | 2008-05-06 | Lsi Logic Corporation | Test vehicle data analysis |
| JP5032996B2 (ja) * | 2005-11-28 | 2012-09-26 | 太陽誘電株式会社 | 半導体装置 |
| US7539967B1 (en) | 2006-05-05 | 2009-05-26 | Altera Corporation | Self-configuring components on a device |
| US7526694B1 (en) | 2006-08-03 | 2009-04-28 | Xilinx, Inc. | Integrated circuit internal test circuit and method of testing therewith |
| JP2008082976A (ja) * | 2006-09-28 | 2008-04-10 | Fujitsu Ltd | Fbm生成装置、fbm生成方法 |
| DE102007028802B4 (de) * | 2007-06-22 | 2010-04-08 | Qimonda Ag | Integrierte Logikschaltung und Verfahren zum Herstellen einer integrierten Logikschaltung |
| US9110142B2 (en) * | 2011-09-30 | 2015-08-18 | Freescale Semiconductor, Inc. | Methods and apparatus for testing multiple-IC devices |
| US9998114B2 (en) * | 2013-10-31 | 2018-06-12 | Honeywell International Inc. | Matrix ferrite driver circuit |
| JP6478562B2 (ja) | 2013-11-07 | 2019-03-06 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US9385054B2 (en) * | 2013-11-08 | 2016-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Data processing device and manufacturing method thereof |
| JP6393590B2 (ja) | 2013-11-22 | 2018-09-19 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| JP6444723B2 (ja) | 2014-01-09 | 2018-12-26 | 株式会社半導体エネルギー研究所 | 装置 |
| US9379713B2 (en) | 2014-01-17 | 2016-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Data processing device and driving method thereof |
| JP2015165226A (ja) * | 2014-02-07 | 2015-09-17 | 株式会社半導体エネルギー研究所 | 装置 |
| US9869716B2 (en) | 2014-02-07 | 2018-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Device comprising programmable logic element |
| US9871511B2 (en) | 2014-07-01 | 2018-01-16 | Honeywell International Inc. | Protection switching for matrix of ferrite modules with redundant control |
| KR20170061602A (ko) * | 2015-11-26 | 2017-06-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 전자 기기 |
| CN106653098B (zh) * | 2017-01-04 | 2020-06-16 | 盛科网络(苏州)有限公司 | 针对逻辑和cpu均可读写存储器的测试方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4447881A (en) * | 1980-05-29 | 1984-05-08 | Texas Instruments Incorporated | Data processing system integrated circuit having modular memory add-on capacity |
| US5068823A (en) * | 1988-07-11 | 1991-11-26 | Star Semiconductor Corporation | Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof |
| US5378934A (en) | 1990-09-12 | 1995-01-03 | Hitachi, Ltd. | Circuit having a master-and-slave and a by-pass |
| JP2922060B2 (ja) | 1992-07-27 | 1999-07-19 | 富士通株式会社 | 半導体記憶装置 |
| US5629890A (en) * | 1994-09-14 | 1997-05-13 | Information Storage Devices, Inc. | Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method |
| TW374951B (en) | 1997-04-30 | 1999-11-21 | Toshiba Corp | Semiconductor memory |
| JP3597706B2 (ja) * | 1997-07-25 | 2004-12-08 | 株式会社東芝 | ロジック混載メモリ |
| US6157210A (en) * | 1997-10-16 | 2000-12-05 | Altera Corporation | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
| US6172899B1 (en) * | 1998-05-08 | 2001-01-09 | Micron Technology. Inc. | Static-random-access-memory cell |
| US6072737A (en) * | 1998-08-06 | 2000-06-06 | Micron Technology, Inc. | Method and apparatus for testing embedded DRAM |
| WO2000062339A1 (fr) | 1999-04-14 | 2000-10-19 | Hitachi, Ltd. | Circuit integre semi-conducteur, procede de verification et procede de fabrication d'un tel circuit |
-
2000
- 2000-11-30 JP JP2000364005A patent/JP3980827B2/ja not_active Expired - Fee Related
-
2001
- 2001-03-02 TW TW090104894A patent/TW535279B/zh not_active IP Right Cessation
- 2001-03-09 KR KR1020010012207A patent/KR20010089236A/ko not_active Withdrawn
- 2001-03-12 US US09/803,030 patent/US6601218B2/en not_active Expired - Fee Related
- 2001-04-02 US US09/822,429 patent/US6436741B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160119117A (ko) * | 2014-02-07 | 2016-10-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 장치 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001325800A (ja) | 2001-11-22 |
| JP3980827B2 (ja) | 2007-09-26 |
| TW535279B (en) | 2003-06-01 |
| US20010021558A1 (en) | 2001-09-13 |
| US6436741B2 (en) | 2002-08-20 |
| US6601218B2 (en) | 2003-07-29 |
| US20010022743A1 (en) | 2001-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20010089236A (ko) | 반도체 집적 회로 장치 및 제조 방법 | |
| US6768694B2 (en) | Method of electrically blowing fuses under control of an on-chip tester interface apparatus | |
| JP3588246B2 (ja) | プロセッサ・ベースの組込み自己検査マクロ及び集積回路チップ | |
| US7434129B2 (en) | Partial good integrated circuit and method of testing same | |
| KR100714240B1 (ko) | 반도체 집적회로 및 기록매체 | |
| US7225379B2 (en) | Circuit and method for testing semiconductor device | |
| US6691252B2 (en) | Cache test sequence for single-ported row repair CAM | |
| KR100900921B1 (ko) | 반도체 장치 | |
| US5917764A (en) | Semiconductor memory device | |
| JP4809568B2 (ja) | メモリ自己テストの方法と装置 | |
| JPWO1998047152A1 (ja) | 半導体集積回路およびメモリの検査方法 | |
| JPS6231439B2 (enExample) | ||
| JPH08147995A (ja) | 半導体記憶装置 | |
| US7047461B2 (en) | Semiconductor integrated circuit device with test data output nodes for parallel test results output | |
| US20050166111A1 (en) | Memory built-in self test circuit with full error mapping capability | |
| JP2001006395A (ja) | 半導体メモリ装置及びそのテストモード時の読出方法 | |
| US7246279B2 (en) | Static random access memory (SRAM) unit and method for operating the same | |
| JPWO2000062339A1 (ja) | 半導体集積回路およびそのテスト方法並びに製造方法 | |
| CN110415751B (zh) | 一种可参数化配置的存储器内建自测试电路 | |
| JPH0750450B2 (ja) | 冗長メモリアレイ | |
| US7013414B2 (en) | Test method and test system for semiconductor device | |
| US6662315B1 (en) | Parallel test in asynchronous memory with single-ended output path | |
| JP4176944B2 (ja) | 半導体集積回路及び記録媒体 | |
| US20080155363A1 (en) | Bist circuit device and self test method thereof | |
| JPH11213700A (ja) | 組込みメモリ用のプロセッサ・ベースのbist |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20010309 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |