KR20010089236A - 반도체 집적 회로 장치 및 제조 방법 - Google Patents

반도체 집적 회로 장치 및 제조 방법 Download PDF

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Publication number
KR20010089236A
KR20010089236A KR1020010012207A KR20010012207A KR20010089236A KR 20010089236 A KR20010089236 A KR 20010089236A KR 1020010012207 A KR1020010012207 A KR 1020010012207A KR 20010012207 A KR20010012207 A KR 20010012207A KR 20010089236 A KR20010089236 A KR 20010089236A
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KR
South Korea
Prior art keywords
circuit
memory
signal
test
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020010012207A
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English (en)
Korean (ko)
Inventor
사또마사유끼
우찌야마구니오
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가나이 쓰토무
Publication of KR20010089236A publication Critical patent/KR20010089236A/ko
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0401Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1206Location of test circuitry on chip or wafer

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
KR1020010012207A 2000-03-10 2001-03-09 반도체 집적 회로 장치 및 제조 방법 Withdrawn KR20010089236A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000066335 2000-03-10
JP2000-066335 2000-03-10
JP2000364005A JP3980827B2 (ja) 2000-03-10 2000-11-30 半導体集積回路装置および製造方法
JP2000-364005 2000-11-30

Publications (1)

Publication Number Publication Date
KR20010089236A true KR20010089236A (ko) 2001-09-29

Family

ID=26587168

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010012207A Withdrawn KR20010089236A (ko) 2000-03-10 2001-03-09 반도체 집적 회로 장치 및 제조 방법

Country Status (4)

Country Link
US (2) US6601218B2 (enExample)
JP (1) JP3980827B2 (enExample)
KR (1) KR20010089236A (enExample)
TW (1) TW535279B (enExample)

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KR20160119117A (ko) * 2014-02-07 2016-10-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 장치

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US20030149926A1 (en) * 2002-02-07 2003-08-07 Rajan Krishna B. Single scan chain in hierarchiacally bisted designs
JP3934434B2 (ja) * 2002-02-19 2007-06-20 富士通株式会社 回路の試験装置
JP2003303499A (ja) * 2002-04-08 2003-10-24 Mitsubishi Electric Corp 半導体集積回路
US6925406B2 (en) * 2002-06-21 2005-08-02 Teseda Corporation Scan test viewing and analysis tool
US6952623B2 (en) * 2002-07-02 2005-10-04 Texas Instruments, Inc. Permanent chip ID using FeRAM
JP2004047596A (ja) * 2002-07-10 2004-02-12 Renesas Technology Corp 半導体装置の製造方法
US7295028B2 (en) * 2002-08-30 2007-11-13 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and memory test method
US6917215B2 (en) * 2002-08-30 2005-07-12 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and memory test method
US7096386B2 (en) * 2002-09-19 2006-08-22 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit having functional modules each including a built-in self testing circuit
US7007211B1 (en) 2002-10-04 2006-02-28 Cisco Technology, Inc. Testing self-repairing memory of a device
DE10259282B4 (de) * 2002-12-18 2005-05-19 Texas Instruments Deutschland Gmbh Batteriebetriebener Verbrauchszähler mit einem Mikro-Controller und Bausteinen zur Realisierung einer Zustandsmaschine
JP4167497B2 (ja) * 2003-01-17 2008-10-15 株式会社ルネサステクノロジ 半導体集積回路及びその試験を行う試験システム
WO2004079382A1 (en) * 2003-03-04 2004-09-16 Koninklijke Philips Electronics N.V. Automatically detecting and routing of test signals
US20040180561A1 (en) * 2003-03-12 2004-09-16 Nexcleon, Inc. Structures for testing circuits and methods for fabricating the structures
US7308627B2 (en) * 2003-04-16 2007-12-11 Lsi Corporation Self-timed reliability and yield vehicle with gated data and clock
US6861864B2 (en) * 2003-04-16 2005-03-01 Lsi Logic Corporation Self-timed reliability and yield vehicle array
JP4308637B2 (ja) * 2003-12-17 2009-08-05 株式会社日立製作所 半導体試験装置
TWI369504B (en) * 2004-07-27 2012-08-01 Lsi Corp Methods of locating a fault within an array of integrated circuits, methods of testing an array of interconnect modules, and speed fault test vehicles for locating a fault within an array of interconnect modules
US7284213B2 (en) * 2005-04-08 2007-10-16 Lsi Corporation Defect analysis using a yield vehicle
US7370257B2 (en) * 2005-04-08 2008-05-06 Lsi Logic Corporation Test vehicle data analysis
JP5032996B2 (ja) * 2005-11-28 2012-09-26 太陽誘電株式会社 半導体装置
US7539967B1 (en) 2006-05-05 2009-05-26 Altera Corporation Self-configuring components on a device
US7526694B1 (en) 2006-08-03 2009-04-28 Xilinx, Inc. Integrated circuit internal test circuit and method of testing therewith
JP2008082976A (ja) * 2006-09-28 2008-04-10 Fujitsu Ltd Fbm生成装置、fbm生成方法
DE102007028802B4 (de) * 2007-06-22 2010-04-08 Qimonda Ag Integrierte Logikschaltung und Verfahren zum Herstellen einer integrierten Logikschaltung
US9110142B2 (en) * 2011-09-30 2015-08-18 Freescale Semiconductor, Inc. Methods and apparatus for testing multiple-IC devices
US9998114B2 (en) * 2013-10-31 2018-06-12 Honeywell International Inc. Matrix ferrite driver circuit
JP6478562B2 (ja) 2013-11-07 2019-03-06 株式会社半導体エネルギー研究所 半導体装置
US9385054B2 (en) * 2013-11-08 2016-07-05 Semiconductor Energy Laboratory Co., Ltd. Data processing device and manufacturing method thereof
JP6393590B2 (ja) 2013-11-22 2018-09-19 株式会社半導体エネルギー研究所 半導体装置
JP6444723B2 (ja) 2014-01-09 2018-12-26 株式会社半導体エネルギー研究所 装置
US9379713B2 (en) 2014-01-17 2016-06-28 Semiconductor Energy Laboratory Co., Ltd. Data processing device and driving method thereof
JP2015165226A (ja) * 2014-02-07 2015-09-17 株式会社半導体エネルギー研究所 装置
US9869716B2 (en) 2014-02-07 2018-01-16 Semiconductor Energy Laboratory Co., Ltd. Device comprising programmable logic element
US9871511B2 (en) 2014-07-01 2018-01-16 Honeywell International Inc. Protection switching for matrix of ferrite modules with redundant control
KR20170061602A (ko) * 2015-11-26 2017-06-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
CN106653098B (zh) * 2017-01-04 2020-06-16 盛科网络(苏州)有限公司 针对逻辑和cpu均可读写存储器的测试方法

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US5378934A (en) 1990-09-12 1995-01-03 Hitachi, Ltd. Circuit having a master-and-slave and a by-pass
JP2922060B2 (ja) 1992-07-27 1999-07-19 富士通株式会社 半導体記憶装置
US5629890A (en) * 1994-09-14 1997-05-13 Information Storage Devices, Inc. Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method
TW374951B (en) 1997-04-30 1999-11-21 Toshiba Corp Semiconductor memory
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US6157210A (en) * 1997-10-16 2000-12-05 Altera Corporation Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits
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US6072737A (en) * 1998-08-06 2000-06-06 Micron Technology, Inc. Method and apparatus for testing embedded DRAM
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160119117A (ko) * 2014-02-07 2016-10-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 장치

Also Published As

Publication number Publication date
JP2001325800A (ja) 2001-11-22
JP3980827B2 (ja) 2007-09-26
TW535279B (en) 2003-06-01
US20010021558A1 (en) 2001-09-13
US6436741B2 (en) 2002-08-20
US6601218B2 (en) 2003-07-29
US20010022743A1 (en) 2001-09-20

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20010309

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid