TW535279B - Semiconductor integrated circuit and its manufacturing method - Google Patents
Semiconductor integrated circuit and its manufacturing method Download PDFInfo
- Publication number
- TW535279B TW535279B TW090104894A TW90104894A TW535279B TW 535279 B TW535279 B TW 535279B TW 090104894 A TW090104894 A TW 090104894A TW 90104894 A TW90104894 A TW 90104894A TW 535279 B TW535279 B TW 535279B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit
- memory
- address
- signal
- test
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000015654 memory Effects 0.000 claims abstract description 257
- 238000012360 testing method Methods 0.000 claims abstract description 184
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000011159 matrix material Substances 0.000 claims description 73
- 230000006870 function Effects 0.000 claims description 23
- 238000013500 data storage Methods 0.000 claims description 16
- 238000012545 processing Methods 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 238000013461 design Methods 0.000 claims description 12
- 230000000246 remedial effect Effects 0.000 claims description 5
- 239000011257 shell material Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 31
- 230000000875 corresponding effect Effects 0.000 description 24
- 238000010586 diagram Methods 0.000 description 23
- 230000002950 deficient Effects 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 17
- 239000000047 product Substances 0.000 description 15
- 230000007547 defect Effects 0.000 description 11
- 230000002079 cooperative effect Effects 0.000 description 10
- 102100025677 Alkaline phosphatase, germ cell type Human genes 0.000 description 6
- 101000574440 Homo sapiens Alkaline phosphatase, germ cell type Proteins 0.000 description 6
- 230000001939 inductive effect Effects 0.000 description 6
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- 238000004364 calculation method Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 101100386518 Caenorhabditis elegans dbl-1 gene Proteins 0.000 description 4
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- 101100268653 Leptosphaeria maculans (strain JN3 / isolate v23.1.3 / race Av1-4-5-6-7-8) abl5 gene Proteins 0.000 description 4
- 102100022596 Tyrosine-protein kinase ABL1 Human genes 0.000 description 4
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- 238000009434 installation Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 101100084025 Mus musculus Alpg gene Proteins 0.000 description 2
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- 238000011161 development Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 241000270708 Testudinidae Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
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- 238000004880 explosion Methods 0.000 description 1
- 210000003205 muscle Anatomy 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005067 remediation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
Landscapes
- Tests Of Electronic Circuits (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000066335 | 2000-03-10 | ||
| JP2000364005A JP3980827B2 (ja) | 2000-03-10 | 2000-11-30 | 半導体集積回路装置および製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW535279B true TW535279B (en) | 2003-06-01 |
Family
ID=26587168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW090104894A TW535279B (en) | 2000-03-10 | 2001-03-02 | Semiconductor integrated circuit and its manufacturing method |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6601218B2 (enExample) |
| JP (1) | JP3980827B2 (enExample) |
| KR (1) | KR20010089236A (enExample) |
| TW (1) | TW535279B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI666458B (zh) * | 2014-02-07 | 2019-07-21 | 日商半導體能源研究所股份有限公司 | 包括可程式邏輯元件和可程式開關的裝置 |
Families Citing this family (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6417695B1 (en) * | 2001-03-15 | 2002-07-09 | Micron Technology, Inc. | Antifuse reroute of dies |
| JP4339534B2 (ja) * | 2001-09-05 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | メモリチップとロジックチップとを搭載し,メモリチップの試験を可能にした半導体装置 |
| US20030149926A1 (en) * | 2002-02-07 | 2003-08-07 | Rajan Krishna B. | Single scan chain in hierarchiacally bisted designs |
| JP3934434B2 (ja) * | 2002-02-19 | 2007-06-20 | 富士通株式会社 | 回路の試験装置 |
| JP2003303499A (ja) * | 2002-04-08 | 2003-10-24 | Mitsubishi Electric Corp | 半導体集積回路 |
| US6925406B2 (en) * | 2002-06-21 | 2005-08-02 | Teseda Corporation | Scan test viewing and analysis tool |
| US6952623B2 (en) * | 2002-07-02 | 2005-10-04 | Texas Instruments, Inc. | Permanent chip ID using FeRAM |
| JP2004047596A (ja) * | 2002-07-10 | 2004-02-12 | Renesas Technology Corp | 半導体装置の製造方法 |
| US6917215B2 (en) * | 2002-08-30 | 2005-07-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit and memory test method |
| US7295028B2 (en) * | 2002-08-30 | 2007-11-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit and memory test method |
| US7096386B2 (en) * | 2002-09-19 | 2006-08-22 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit having functional modules each including a built-in self testing circuit |
| US7007211B1 (en) | 2002-10-04 | 2006-02-28 | Cisco Technology, Inc. | Testing self-repairing memory of a device |
| DE10259282B4 (de) * | 2002-12-18 | 2005-05-19 | Texas Instruments Deutschland Gmbh | Batteriebetriebener Verbrauchszähler mit einem Mikro-Controller und Bausteinen zur Realisierung einer Zustandsmaschine |
| JP4167497B2 (ja) * | 2003-01-17 | 2008-10-15 | 株式会社ルネサステクノロジ | 半導体集積回路及びその試験を行う試験システム |
| CN1756962A (zh) * | 2003-03-04 | 2006-04-05 | 皇家飞利浦电子股份有限公司 | 测试信号的自动检测和路由 |
| US20040180561A1 (en) * | 2003-03-12 | 2004-09-16 | Nexcleon, Inc. | Structures for testing circuits and methods for fabricating the structures |
| US6861864B2 (en) * | 2003-04-16 | 2005-03-01 | Lsi Logic Corporation | Self-timed reliability and yield vehicle array |
| US7308627B2 (en) * | 2003-04-16 | 2007-12-11 | Lsi Corporation | Self-timed reliability and yield vehicle with gated data and clock |
| JP4308637B2 (ja) * | 2003-12-17 | 2009-08-05 | 株式会社日立製作所 | 半導体試験装置 |
| TWI369504B (en) * | 2004-07-27 | 2012-08-01 | Lsi Corp | Methods of locating a fault within an array of integrated circuits, methods of testing an array of interconnect modules, and speed fault test vehicles for locating a fault within an array of interconnect modules |
| US7284213B2 (en) * | 2005-04-08 | 2007-10-16 | Lsi Corporation | Defect analysis using a yield vehicle |
| US7370257B2 (en) * | 2005-04-08 | 2008-05-06 | Lsi Logic Corporation | Test vehicle data analysis |
| JP5032996B2 (ja) * | 2005-11-28 | 2012-09-26 | 太陽誘電株式会社 | 半導体装置 |
| US7539967B1 (en) | 2006-05-05 | 2009-05-26 | Altera Corporation | Self-configuring components on a device |
| US7526694B1 (en) * | 2006-08-03 | 2009-04-28 | Xilinx, Inc. | Integrated circuit internal test circuit and method of testing therewith |
| JP2008082976A (ja) * | 2006-09-28 | 2008-04-10 | Fujitsu Ltd | Fbm生成装置、fbm生成方法 |
| DE102007028802B4 (de) * | 2007-06-22 | 2010-04-08 | Qimonda Ag | Integrierte Logikschaltung und Verfahren zum Herstellen einer integrierten Logikschaltung |
| US9110142B2 (en) * | 2011-09-30 | 2015-08-18 | Freescale Semiconductor, Inc. | Methods and apparatus for testing multiple-IC devices |
| US9998114B2 (en) * | 2013-10-31 | 2018-06-12 | Honeywell International Inc. | Matrix ferrite driver circuit |
| JP6478562B2 (ja) | 2013-11-07 | 2019-03-06 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US9385054B2 (en) * | 2013-11-08 | 2016-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Data processing device and manufacturing method thereof |
| JP6393590B2 (ja) * | 2013-11-22 | 2018-09-19 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| JP6444723B2 (ja) | 2014-01-09 | 2018-12-26 | 株式会社半導体エネルギー研究所 | 装置 |
| US9379713B2 (en) | 2014-01-17 | 2016-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Data processing device and driving method thereof |
| JP2015165226A (ja) * | 2014-02-07 | 2015-09-17 | 株式会社半導体エネルギー研究所 | 装置 |
| JP6545970B2 (ja) | 2014-02-07 | 2019-07-17 | 株式会社半導体エネルギー研究所 | 装置 |
| US9871511B2 (en) | 2014-07-01 | 2018-01-16 | Honeywell International Inc. | Protection switching for matrix of ferrite modules with redundant control |
| KR20170061602A (ko) * | 2015-11-26 | 2017-06-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 전자 기기 |
| CN106653098B (zh) * | 2017-01-04 | 2020-06-16 | 盛科网络(苏州)有限公司 | 针对逻辑和cpu均可读写存储器的测试方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4447881A (en) * | 1980-05-29 | 1984-05-08 | Texas Instruments Incorporated | Data processing system integrated circuit having modular memory add-on capacity |
| US5068823A (en) * | 1988-07-11 | 1991-11-26 | Star Semiconductor Corporation | Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof |
| US5378934A (en) | 1990-09-12 | 1995-01-03 | Hitachi, Ltd. | Circuit having a master-and-slave and a by-pass |
| JP2922060B2 (ja) | 1992-07-27 | 1999-07-19 | 富士通株式会社 | 半導体記憶装置 |
| US5629890A (en) * | 1994-09-14 | 1997-05-13 | Information Storage Devices, Inc. | Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method |
| TW374951B (en) | 1997-04-30 | 1999-11-21 | Toshiba Corp | Semiconductor memory |
| JP3597706B2 (ja) * | 1997-07-25 | 2004-12-08 | 株式会社東芝 | ロジック混載メモリ |
| US6157210A (en) * | 1997-10-16 | 2000-12-05 | Altera Corporation | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
| US6172899B1 (en) * | 1998-05-08 | 2001-01-09 | Micron Technology. Inc. | Static-random-access-memory cell |
| US6072737A (en) * | 1998-08-06 | 2000-06-06 | Micron Technology, Inc. | Method and apparatus for testing embedded DRAM |
| WO2000062339A1 (fr) | 1999-04-14 | 2000-10-19 | Hitachi, Ltd. | Circuit integre semi-conducteur, procede de verification et procede de fabrication d'un tel circuit |
-
2000
- 2000-11-30 JP JP2000364005A patent/JP3980827B2/ja not_active Expired - Fee Related
-
2001
- 2001-03-02 TW TW090104894A patent/TW535279B/zh not_active IP Right Cessation
- 2001-03-09 KR KR1020010012207A patent/KR20010089236A/ko not_active Withdrawn
- 2001-03-12 US US09/803,030 patent/US6601218B2/en not_active Expired - Fee Related
- 2001-04-02 US US09/822,429 patent/US6436741B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI666458B (zh) * | 2014-02-07 | 2019-07-21 | 日商半導體能源研究所股份有限公司 | 包括可程式邏輯元件和可程式開關的裝置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010089236A (ko) | 2001-09-29 |
| US6601218B2 (en) | 2003-07-29 |
| JP3980827B2 (ja) | 2007-09-26 |
| JP2001325800A (ja) | 2001-11-22 |
| US6436741B2 (en) | 2002-08-20 |
| US20010021558A1 (en) | 2001-09-13 |
| US20010022743A1 (en) | 2001-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |